MCP37D11-80ESLASHTE datasheet(52/136 Pages) MICROCHIP

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MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

DS20006381A-page 52

 2020 Microchip Technology Inc.

4.8.4

DIGITAL DOWN-CONVERSION

The Digital Down-Conversion (DDC) feature is

available in single, dual, and CW octal-channel modes.

This feature can be optionally combined with the

decimation filter and used to:

• translate the input frequency spectrum to a lower

frequency band

• remove the unwanted out-of-band portion

• output the resulting signal as either I/Q data or as

a real signal centered at 25% of the output data

rate.

Figure 4-17

and

Figure 4-18

show

the

DDC

configuration for single- and dual-channel DDC mode,

respectively. The DDC includes a 32-bit, complex

numerically controlled oscillator (NCO), a selectable

(high/low) half-band filter, optional decimation, and two

output modes (I/Q or fS/8).

Frequency translation is accomplished with the NCO.

The NCO frequency is programmable from 0 Hz to fS.

Phase and amplitude dither can be enabled to improve

spurious performance of the NCO.

This DDC feature can be used in a variety of high-

speed signal-processing applications, including digital

radio, sonar, radar, cable modems, digital video, MRI

imaging, etc.

Example:

If the ADC is sampling an input at 80 Msps, but the user

is only interested in a 2.5 MHz span which is centered

at 20 MHz, the digital down-conversion may be used to

mix the sampled ADC data with 20 MHz to convert it to

DC. The resulting signal can then be decimated by 16x

such that the bandwidth of the ADC output is 2.5 MHz

(80 Msps/16x decimation gives 5 Msps with 2.5 MHz

Nyquist bandwidth). If fS/8 mode is selected, then a

single 10 Msps channel is output (corresponding to 5

MHz Nyquist bandwidth), where 2.5 MHz in the output

data corresponds to 20 MHz at the ADC input. If I/Q

mode is selected, then two 5 Msps channels are

output, where DC corresponds to 20 MHz and the

channels represent in-phase (I) and quadrature (Q)

components of the down-conversion.

4.8.4.1

Single-Channel DDC

Figure 4-17

shows

the

single-channel

DDC

configuration. Each of these processing sub-blocks are

individually controlled. Examples of setting registers for

selected output type are shown in Tables 4-17 and 4-18.

FIGURE 4-17:

Simplified DDC Block Diagram for Single-Channel Mode. See Tables 4-17 and 4-18

for Using This DDC Block.

Half-Band Filter A

LP/HP

NCO (32-bit)

CH. A

Down-Converting and Decimation

HBFILTER_A

Decimation and Output Frequency Translation

FIR A

Decimation Filter

(Note 2)

(Note 1)

Real

(Note 3)

EN_DDC2

EN_DDC_FS/8

NCO (

)

EN_DDC1

fS/8

DER

EN_NCO

(Note 4)

(Note 5)

ADC DATA

COS

SIN

FIR_A<8:1>

FIR_B<7:0>

FIR B

Decimation Filter

I or IDEC

Q or QDEC

RealDEC

Note 1: See Address 0x80 - 0x81 (Registers 5-41 – 5-42) for the control parameters.

2: See Figure 4-19 for details of NCO control block.

3: Half-band Filter A includes a single- stage decimation filter.

4: See Figure 4-16 for details.

5: Switches are closed if decimation filter is not used, and open if decimation filter is used.

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