MCP37D11-80ESLASHTE datasheet(71/136 Pages) MICROCHIP

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 2020 Microchip Technology Inc.

DS20006381A-page 71

MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

5.0

SERIAL PERIPHERAL

INTERFACE (SPI)

The user can configure the ADC for specific functions

or optimized performance by setting the device’s

internal registers through the serial peripheral interface

(SPI). The SPI communication uses three pins: CS,

SCLK and SDIO. Table 5-1 summarizes the SPI pin

functions. The SCLK is used as a serial timing clock

and can be used up to 50 MHz. SDIO (Serial Data

Input/Output) is a dual-purpose pin that allows data to

be sent or read from the internal registers. The Chip

Select pin (CS) enables SPI communication when

active-low. The falling edge of CS followed by a rising

edge of SCLK determines the start of the SPI

communication. When CS is tied to high, SPI

communication is disabled and the SPI pins are placed

in high-impedance mode. The internal registers are

accessible by their address.

Figures 5-1 and 5-2 show the SPI data communication

protocols for this device with MSb-first and LSb-first

options, respectively. It consists of:

• 16-bit wide instruction header + Data byte 1 +

Data byte 2 + . . . + Data Byte N

Table 5-2 summarizes the bit functions. The R/W bit of

the instruction header indicates whether the command

is a read (‘1’) or a write (‘0’):

•If the R/W bit is ‘1’, the SDIO pin changes

direction from an input (SDI) to an output (SDO)

after the 16-bit wide instruction header.

By selecting the R/W bit, the user can write the register

or read back the register contents. The W1 and W2 bits

in the instruction header indicate the number of data

bytes to transmit or receive in the following data frame.

Bits A2 – A0 are the SPI device address bits. These

bits are used when multiple devices are used in the

same SPI bus. A2 is internally hardcoded to ‘0’. Bits A1

and A0 correspond to the logic level of the ADR1 and

ADR0 pins, respectively.

The R9 – R0 bits represent the starting address of the

Configuration register to write or read. The data bytes

following the instruction header are the register data.

All register data is eight bits wide. Data can be sent in

MSb-first mode (default) or in LSb-first mode, which is

determined by the <LSb_ FIRST> bit setting in Address

0x00 (Register 5-1). In Write mode, the data is clocked

in at the rising edge of the SCLK. In the Read mode, the

data is clocked out at the falling edge of the SCLK.

Note 1: The register address counter is incremented

by one per step. The counter does not

automatically reset to 0x00 after reaching the

last address (0x15D). Be aware that the user

registers are not sequentially allocated.

TABLE 5-1:

SPI PIN FUNCTIONS

Name

Descriptions

Chip Select pin. SPI mode is initiated at

the falling edge. It needs to maintain

active-low for the entire period of the

SPI communication. The device exits the

SPI communication at the rising edge.

SCLK

Serial clock input pin.

• Writing to the device: Data is latched

at the rising edge of SCLK

• Reading from the device: Data is

latched at the falling edge of SCLK

SDIO

Serial data input/output pin. This pin is

initially an input pin (SDI) during the first

16-bit instruction header. After the

instruction header, its I/O status can be

changed depending on the R/W bit:

•if R/W = 0: Data input pin (SDI) for

writing

•if R/W = 1: Data output pin (SDO) for

reading

TABLE 5-2:

SPI DATA PROTOCOL BIT

FUNCTIONS

Bit Name

Descriptions

R/W

1 = Read Mode

0 = Write Mode

W1, W0

(Data

Length)

00 = Data for one register (1 byte)

01 = Data for two registers (2 bytes)

10 = Data for three registers (3 bytes)

11 = Continuous reading or writing by

clocking SCLK(1)

A2 - A0

Device SPI Address for multiple

devices in SPI bus

A2: Internally hardcoded to ‘0’

A1: Logic level of ADR1 pin

A0: Logic level of ADR0 pin

R9 - R0

Address of starting register

D7 - D0

depending on the LSb_FIRST bit

setting in 0x00

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