MCP37D11-80ESLASHTE datasheet(67/136 Pages) MICROCHIP

67 / 136 page

 2020 Microchip Technology Inc.

DS20006381A-page 67

MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

4.12.10

DIGITAL OUTPUT RANDOMIZER

Depending on PCB layout considerations and power

supply coupling, SFDR may be improved by

decorrelating the ADC input from the ADC digital output

data. The device includes an output data randomizer

option. When this option is enabled, the digital output is

randomized by applying an exclusive-OR logic

operation between the LSb (D0) and all other data

output bits.

To decode the randomized data, the reverse operation

is applied: an exclusive-OR operation is applied

between the LSb (D0) and all other bits. The DCLK,

OVR, WCK and LSb (D0) outputs are not affected.

Figure 4-26 shows the block diagram of the data ran-

domizer and decoder logic. The output randomizer is

enabled by setting the EN_OUT_RANDOM bit in

Address 0x07 (Register 5-5).

FIGURE 4-26:

Logic Diagram for Digital Output Randomizer and Decoder.

4.12.11

OUTPUT DISABLE

The digital output can be disabled by setting

OUTPUT_MODE<1:0>

00 in Address 0x62

(Register 5-20). All digital outputs are disabled,

including OVR, WCK, DCLK, etc.

4.12.12

OUTPUT TEST PATTERNS

To facilitate testing of the I/O interface, the device can

produce various predefined or user-defined patterns on

the digital outputs. See TEST_PATTERNS<2:0> in

Address 0x62 (Register 5-20) for the predefined test

patterns. For the user-defined patterns, Addresses

0x74 – 0x77

(Registers 5-29 – 5-32)

can

programmed using the SPI interface. When an output

test mode is enabled, the ADC’s analog section can still

be operational, but does not drive the digital outputs. The

outputs are driven only with the selected test pattern.

WCK

DCLK

OVR

WCK

DCLK

OVR

Data Acquisition Device

(a) Data Randomizer

(b) Data Decoder

DCLK

WCK

OVR

EN_OUT_RANDOM

MCP37D11-80

Q11

Q10

Q11

Q10

Q11

Q10

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