MCP37D11-80ESLASHTE datasheet(92/136 Pages) MICROCHIP

92 / 136 page

MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

DS20006381A-page 92

 2020 Microchip Technology Inc.

ADDRESS 0X66 – DIGITAL OFFSET CORRECTION (LOWER BYTE)

R/W-0

DIG_OFFSET_GLOBAL<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

DIG_OFFSET_GLOBAL<7:0>: Lower byte of DIG_OFFSET_GLOBAL<15:0> for all channels(-)

0000-0000 = Default

-Offset is added to the ADC output. Setting is two’s complement using two combined registers (16-bits wide).

Setting range: (-215 to 215 - 1) x 0.125 LSb(s)

ADDRESS 0X67 – DIGITAL OFFSET CORRECTION (UPPER BYTE)

R/W-0

DIG_OFFSET_GLOBAL<15:8>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

DIG_OFFSET_GLOBAL<15:8>: Upper byte of DIG_OFFSET_GLOBAL<15:0> for all channels(1)

0000-0000 = Default

Note

See

Note - in Address 0x66 (Register 5-24)

ADDRESS 0X68 – WCK AND OVR BIT CONTROL

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

FCB<5:2>

POL_WCK_OVR EN_WCK_OVR

FCB<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

FCB<5:2>: Factory-controlled bits. This is not for the user. Do not change default settings.

bit 3

POL_WCK_OVR: Polarity control for WCK and OVR bit pair in LVDS mode

1 = Inverted

0 =Not inverted (Default)

bit 2

EN_WCK_OVR: Enable WCK and OVR output bit pair

1 = Enabled (Default)

0 =Disabled

bit 1-0

FCB<1:0>: Factory-controlled bits. This is not for the user. Do not change default settings.

MCP37D11-80E/TE Datasheet(PDF) 92 Page - Microchip Technology

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