MCP37D11-80ESLASHTE datasheet(39/136 Pages) MICROCHIP

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 2020 Microchip Technology Inc.

DS20006381A-page 39

MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

4.6.1

CLOCK JITTER AND SNR

PERFORMANCE

In a high-speed pipelined ADC, the SNR performance

is directly limited by thermal noise and clock jitter.

Thermal noise is independent of input clock and

dominant term at low-input frequency. On the other

hand, the clock jitter becomes a dominant term as input

frequency increases. Equation 4-2 shows the SNR

jitter component, which is expressed in terms of the

input frequency (fIN) and the total amount of clock jitter

(TJitter), where TJitter is a sum of the following two

components:

• Input clock jitter (phase noise)

• Internal aperture jitter (due to noise of the clock

input buffer).

EQUATION 4-2:

SNR VS.CLOCK JITTER

The clock jitter can be minimized by using a high-

quality clock source and jitter cleaners as well as a

band-pass filter at the external clock input, while a

faster clock slew rate improves the ADC aperture jitter.

With a fixed amount of clock jitter, the SNR degrades

as the input frequency increases. This is illustrated in

Figure 4-10. If the input frequency increases from

10 MHz to 20 MHz, the maximum achievable SNR

degrades about 6 dB. For every decade (e.g. 10 MHz

to 100 MHz), the maximum achievable SNR due to

clock jitter is reduced by 20 dB.

FIGURE 4-10:

SNR vs. Clock Jitter.

SNRJitter dBc



20 log10



–

 f



Jitter



where the total jitter term (Tjitter) is given by:

TJitter

tJitter Clock Input



tAperture ADC



100

120

140

160

100

1000

Input Frequency (f

IN, MHz)

Jitter = 1 ps

Jitter = 0.5 ps

Jitter = 0.25 ps

Jitter = 0.125 ps

Jitter = 0.0625 ps

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