MCP37D11-80ESLASHTE datasheet(46/136 Pages) MICROCHIP

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MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

DS20006381A-page 46

 2020 Microchip Technology Inc.

4.8

Digital Signal Post-Processing

(DSPP) Options

While the device converts the analog input signals to

digital output codes, the user can enable various digital

signal post-processing (DSPP) options for special

applications. These options are individually enabled or

disabled by setting the Configuration bits. Table 4-9

summarizes the digital signal post-processing (DSPP)

options that are available for each device family.

4.8.1

FRACTIONAL DELAY RECOVERY

FOR DUAL- AND OCTAL-CHANNEL

MODES

The fractional delay recovery (FDR) feature is available

in dual and octal-channel modes only. When FDR is

enabled,

the

built-in

high-order,

band-limited

interpolation filter compensates for the time delay

between input samples of different channels. Due to

the finite bandwidth of the interpolation filter, the

fractional delay recovery is not guaranteed for input

frequencies near the Nyquist frequency (fS/2). For

example, in dual-channel mode, FDR can operate

correctly for input frequencies in the range from 0 to

0.45*fS (or from 0.55*fs to fS if the input is in the 2nd

Nyquist band). In octal-channel mode, FDR can

operate correctly for input frequencies in the range

from 0 to 0.38*fS. See Table 4-11 for the summary of

the input bandwidth requirement for FDR. The FDR

process takes place in the digital domain and requires

59 clock cycles of processing time. Therefore, the

output data latency is also increased by 59 clock

periods.

Figure 4-12 shows the simplified block diagram for the

ADC output data path with FDR. The related

Configuration register bits are listed in Table 4-10.

Table 4-11 shows the input bandwidth limits of the FDR

feature for distortion less than 0.1 mdB (0.1 × 10-3 dB),

where fS is the sampling frequency per channel.

Figures 4-13 and 4-14 show the responses of the dual-

channel and octal-channel FDRs, respectively.

FIGURE 4-12:

Simplified Block Diagram for

ADC Output Data Path with Fractional Delay

Recovery Option. Note that Fractional Delay

Recovery occurs prior to other DSPP features.

TABLE 4-9:

DIGITAL SIGNAL POST PROCESSING (DSPP) OPTIONS

Digital Signal Post Processing Option

Available Operating Mode

Fractional Delay Recovery (FDR)

Dual and octal-channel modes

FIR Decimation Filters

• Single and dual-channel modes

• CW octal-channel mode

• DDC for I and Q data

Noise-Shaping Requantizer (NSR)

Single and dual-channel modes

Digital Gain and Offset correction per channel Available for all channels

Digital-Down Conversion (DDC)

• Single and dual-channel modes

• CW octal-channel mode

Continuous Wave (CW) Beamforming

CW octal-channel mode

Fractional Delay

Recovery

(FDR)

ADC Output for

dual or octal-channel

FDR Control

ADC output data after

sampling time delay between

channels is removed.

FIR

Decimation Filters

Digital

Down-Conversion (DDC)

Beamforming

Noise-Shaping

Requantizer

(NSR)

Digital Gain/Offset

Correction per Channel

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