MCP37D31-80ESLASHTE datasheet(21/141 Pages) MICROCHIP

21 / 141 page

MCP37D31-80 AND MCP37D21-80

DS20006382A-page 21

 2020 Microchip Technology Inc.

FIGURE 2-4:

Timing Diagram - LVDS Serial Output in Octal-Channel Mode. This output is available

for octal-channel with 16-bit mode only. Note that although the eight input channels are sampled

sequentially (auto-scan with 1 cycle separation), all channels are output simultaneously with the MSb (bit

15) synchronized with the rising edge of WCK.

CLK Output:

Input Clock:

Word-CLK/

Over-Range Output:

Ch.0

Ch.1

Ch.0

Ch.7

Latency = L Cycles

tCPD

tDC

tPD

DCLK-

DCLK+

Q-[0]

Q+[0]

WCK/OVR-

WCK/OVR+

b[15]

Ch.0

b[14]

Ch.0

b[1]

Ch.0

b[0]

Ch.0

b[13]

Ch.0

b[15]

Ch.0

b[1]

Ch.0

b[0]

Ch.0

WCK

“1”

OVR

WCK

“1”

OVR

Q-[7]

Q+[7]

b[15]

Ch.7

b[14]

Ch.7

b[1]

Ch.7

b[0]

Ch.7

b[13]

Ch.7

b[15]

Ch.7

b[1]

Ch.7

b[0]

Ch.7

Q-[1]

Q+[1]

b[15]

Ch.1

b[14]

Ch.1

b[1]

Ch.1

b[0]

Ch.1

b[13]

Ch.1

b[15]

Ch.1

b[1]

Ch.1

b[0]

Ch.1

Ch.7

“0”

CLK-

CLK+

Output Data:

Input Signal:

Note: Q+/Q-[7] is the first channel selected data, and Q+/Q-[0] is the last channel selected data.

MCP37D31-80E/TE Datasheet(PDF) 21 Page - Microchip Technology

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