MCP37D31-80ESLASHTE datasheet(36/141 Pages) MICROCHIP

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 2020 Microchip Technology Inc.

DS20006382A-page 36

MCP37D31-80 AND MCP37D21-80

4.0

THEORY OF OPERATION

The MCP37D31-80 and MCP37D21-80 device family

is a high-precision 80 Msps, 16-bit and 14-bit,

respectively, analog-to-digital converter (ADC) with

built-in

features

including

Harmonic

Distortion

Correction (HDC), DAC Noise Cancellation (DNC),

Dynamic Element Matching (DEM) and flash error

calibration.

In addition to the analog-to-digital data conversion, the

device offers various built-in digital signal post-

processing (DSPP) features, such as high-order FIR

decimation filters, Digital Down-Conversion (DDC),

Fractional Delay Recovery (FDR), continuous wave

(CW) beamforming, and digital gain and offset

corrections per individual channel. These built-in

advanced digital signal post-processing sub-blocks,

which are individually controlled using Configuration

applications such as I/Q demodulation, digital down-

conversion, and ultrasound imaging.

When the device is first powered-up, it performs an

internal power-up calibration by itself and runs with

default settings. From this point, the user can configure

the device registers using the SPI command.

The input channel is selected by setting-up the user-

control configuration register bits. In single-channel

operation, one of the 8-analog inputs can be selected.

In multi-channel mode, the inputs are sequentially

multiplexed by the input MUX defined by the scan

order. The input channel selection and the sequential

scan order for the selected input channel are

programmed using the configuration register bits.

The device samples the analog input on the rising edge

of the clock. The digital output code is available after

28 clock cycles of data latency. Latency will increase if

any of the digital signal post-processing (DSPP)

options are enabled.

The output data can be coded in two’s complement or off-

set binary format, and randomized using the user option.

Data can be output using either the CMOS or LVDS (Low-

Voltage Differential Signaling) interface. Serialized LVDS

output is also available in 16-bit octal-channel mode. In

this mode, each input channel is output serially over a

unique LVDS pair.

4.1

ADC Core Architecture

Figure 4-1 shows the simplified block diagram of the

ADC core. The first stage consists of a 17-level flash

ADC, multi-level Digital-to-Analog Converter (DAC)

and a residue amplifier with a gain of 8. Stages 2 to 6

consist of a 9-level (3-bit) flash ADC, multi-level DAC

and a residue amplifier with a gain of 4. The last stage

is a 9-level 3-bit flash ADC. Dither is added in each of

the first three stages.The digital outputs from all seven

stages are combined in a digital error correction logic

block and digitally processed for the final output.

The first three stages include patented digital

calibration features:

• Harmonic Distortion Correction (HDC) algorithm

that digitally measures and cancels ADC errors

arising from distortions introduced by the residue

amplifiers

• DAC Noise Cancellation (DNC) algorithm that

corrects DAC’s nonlinearity errors

FIGURE 4-1:

ADC Core Block Diagram.

Clock Generation

Pipeline

(3-bit)

Stage 1

Pipeline

(2-bit)

Stage 2

Pipeline

(2-bit)

Stage 3

Pipeline

(2-bit)

Stage 4

Pipeline

(2-bit)

Stage 5

Pipeline

Stage 6

3-bit Flash

(3-bit)

Stage 7

Digital Error Correction

MUX

Input

AIN0+

AIN0-

HDC1, DNC1

HDC2, DNC2

HDC3, DNC3

(2-bit)

AIN7+

AIN7-

User-Programmable Options

Programmable Digital Signal Post-Processing (DSPP)

Reference Generator

REF0

REF1

REF0

REF1

16-Bit Digital Output (MCP37D31-80)

14-Bit Digital Output (MCP37D21-80)

MCP37D31-80E/TE Datasheet(PDF) 36 Page - Microchip Technology

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