MCP37D31-80ESLASHTE datasheet(83/141 Pages) MICROCHIP

83 / 141 page

MCP37D31-80 AND MCP37D21-80

DS20006382A-page 83

 2020 Microchip Technology Inc.

ADDRESS 0X01 – NUMBER OF CHANNELS, INDEPENDENCY CONTROL OF OUTPUT

DATA AND CLOCK DIVIDER

R/W-0

R/W-1

EN_DATCLK_IND

FCB<3>

SEL_NCH<2:0>

FCB<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

EN_DATCLK_IND: Enable data and clock divider independently(1)

1 =

Enabled

0 =

Disabled (Default)

bit 6

FCB<3>: Factory-Controlled Bit. This is not for the user. Do not change default setting.

bit 5-3

SEL_NCH<2:0>: Select the total number of input channels to be used(2)

111 = 7 inputs

110 = 6 inputs

101 = 5 inputs

100 = 4 inputs

011 = 3 inputs

010 = 2 inputs

001 = 1 input (Default)

000 = 8 inputs

bit 2-0

FCB<2:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.

Note

EN_DATCLK_IND = 1 enables OUT_CLKRATE<3:0> settings in Address 0x02 (Register 5-3).

See Addresses 0x7D – 0x7F (Registers 5-37 – 5-39) for selecting the input channel order.

MCP37D31-80E/TE Datasheet(PDF) 83 Page - Microchip Technology

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