MCP37D31-80ESLASHTE datasheet(49/141 Pages) MICROCHIP

49 / 141 page

MCP37D31-80 AND MCP37D21-80

DS20006382A-page 49

 2020 Microchip Technology Inc.

TABLE 4-6:

PLL CONTROL REGISTER BITS

Control Parameter

Descriptions

PLL Global Control Bits

EN_PLL

0x59

Master enable bit for the PLL circuit

EN_PLL_OUT

0x5F

Master enable bit for the PLL output

EN_PLL_BIAS

0x5F

Master enable bit for the PLL bias

EN_PLL_REFDIV

0x59

Master enable bit for the PLL reference divider

PLL Block Setting Bits

PLL_REFDIV<9:0>

0x54-0x55 PLL reference divider (R) (See Table 4-8)

PLL_PRE<11:0>

0x56-0x57 PLL prescaler (N) (See Table 4-8)

PLL_CHAGPUMP<3:0>

0x58

PLL charge pump bias current control: from 25 µA to 375 µA, 25 µA per step

PLL_RES<4:0>

0x5A

PLL loop filter resistor value selection (See Table 4-7)

PLL_CAP3<4:0>

0x5B

PLL loop filter capacitor 3 value selection (See Table 4-7)

PLL_CAP2<4:0>

0x5D

PLL loop filter capacitor 2 value selection (See Table 4-7)

PLL_CAP1<4:0>

0x5C

PLL loop filter capacitor 1 value selection (See Table 4-7)

PLL Output Control Bits

PLL_OUTDIV<3:0>

0x55

PLL output divider (See Table 4-8)

DCLK_DLY_PLL<2:0>

0x6D

Delay DCLK output up to 15 cycles of VCO clocks

EN_PLL_CLK

0x6D

EN_PLL_CLK = 1 enable PLL output clock to the ADC circuits

PLL Drift Monitoring Bits

PLL_VCOL_STAT

0xD1

PLL drift status monitoring bit

PLL_VCOH_STAT

0xD1

PLL drift status monitoring bit

PLL Block Calibration Bits

PLL_CAL_TRIG

0x6B

Forcing recalibration of the PLL

SOFT_RESET

0x00

PLL is calibrated when exiting soft reset mode

PLL_CAL_STAT

0xD1

PLL auto-calibration status indication

MCP37D31-80E/TE Datasheet(PDF) 49 Page - Microchip Technology

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