MCP37D31-80ESLASHTE datasheet(69/141 Pages) MICROCHIP

69 / 141 page

MCP37D31-80 AND MCP37D21-80

DS20006382A-page 69

 2020 Microchip Technology Inc.

4.12.3

SERIALIZED LVDS MODE

This output mode is only available for octal-channel

operation with 16-bit data output, and uses eight output

lanes: a single LVDS pair for each channel output as

shown in Figure 2-6.

Each channel’s data is serialized by the data serializer,

and the outputs are available through eight LVDS

output lanes. Each differential LVDS output pair holds

a single input channel's data, and clocks out data with

double data rate (DDR), which is synchronized with

WCK/OVR bit:

• Q7+/Q7- pair: 1st channel selected

• Q6+/Q6- pair: 2nd channel selected

•

• Q0+/Q0- pair: last channel selected

4.12.4

OVERRANGE BIT (OVR)

The input overrange status bit is asserted (logic high)

when the analog input has exceeded the full-scale

range of the ADC in either the positive or negative

direction. In LVDS DDR Output mode, the OVR bit is

multiplexed with the word clock (WCK) output bit such

that OVR is output on the falling edge of the data output

clock and WCK on the rising edge.

The OVR bit has the same pipeline latency as the

ADC data bits. In multi-channel mode, the OVR is out-

put independently for each input channel and is syn-

chronized to the data. In serialized LVDS mode (for

16-bit octal channel), the MSb is asserted coincident

with the WCK rising edge. OVR will be asserted if any

of the channels are overranged, but it does not specify

which channel is overranged. See Address 0x68

(Register 5-26) for OVR and WCK control options.

If DSPP options are enabled, OVR pipeline latency will

be unaffected; however, the data will incur additional

delay. This has the effect of allowing the OVR indicator

to precede the affected data.

4.12.5

WORD CLOCK (WCK)

The word clock output bit indicates the start of a new

data set. In single-channel mode, this bit is disabled

except for I/Q output mode. In DDR output with multi-

channel mode, it is always asserted coincidentally with

the data from the first sampled channel, and

multiplexed with the OVR bit. See Address 0x07

(Register 5-5) and Address 0x68 (Register 5-26) for

OVR and WCK control options.

4.12.6

LVDS OUTPUT POLARITY

CONTROL

In LVDS mode, the output polarity can be controlled

independently

for

each

LVDS

pair.

Table 4-20

summarizes the LVDS output polarity control register bits.

4.12.7

PROGRAMMABLE LVDS OUTPUT

In LVDS mode, the default output driver current is

3.5 mA. This current can be adjusted by using the

LVDS_IMODE<2:0> bit setting in Address 0x63

(Register 5-20). Available output drive currents are

1.8mA, 3.5mA, 5.4mA and 7.2mA.

4.12.8

OPTIONAL LVDS DRIVER

INTERNAL TERMINATION

In most cases, using an external 100Ω termination

resistor will give excellent LVDS signal integrity. In

addition, an optional internal 100Ω termination resistor

can be enabled by setting the LVDS_LOAD bit in

Address 0x63 (Register 5-21). The internal termination

helps absorb any reflections caused by imperfect

impedance termination at the receiver.

4.12.9

OUTPUT DATA AND CLOCK RATES

The user can reduce output data and output clock rates

using Address 0x02 (Register 5-3). When decimation

or digital down-conversion (DDC) is used, the output

data rate has to be reduced to synchronize with the

reduced output clock rate.

4.12.10

PHASE SHIFTING OF OUTPUT

CLOCK (DCLK)

In full-rate CMOS mode, the data output bit transition

occurs at the rising edge of DCLK+, so the falling edge

of DCLK+ can be used to latch the output data.

In double-data-rate LVDS mode, the data transition

occurs at both the rising and falling edges of DCLK+.

For adequate setup and hold time when latching the

data into the external host device, the user can shift the

phase of the digital clock output (DCLK+/DCLK-)

relative to the data output bits.

Note:

Output Data Rate in LVDS Mode: In

octal-channel mode, the input sample rate

per channel is fS/8. Therefore, the output

data rate required to shift out all 16 bits in

DDR is still equivalent to fS. For example,

if fS = 80 Msps, each channel’s sample

rate is fS/8 = 10 Msps, and the output

clock rate (DCLK) for 16-bit DDR output is

80 MHz.

TABLE 4-20:

LVDS OUTPUT POLARITY

CONTROL

Control

Parameter

Descriptions

POL_LVDS<7:0>

0x65

Control polarity of LVDS

data pairs

POL_WCK_OVR

0x68

Control polarity of WCK

and OVR bit pair

POL_DM1DM2

0x68

Control polarity of DM+

and DM- pair

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