MCP37D31-80ESLASHTE datasheet(62/141 Pages) MICROCHIP

62 / 141 page

 2020 Microchip Technology Inc.

DS20006382A-page 62

MCP37D31-80 AND MCP37D21-80

TABLE 4-16:

MODE EXAMPLE

FIR A Filter

FIR B Filter DDC1

DDC2

Dual-Channel

DSPP

Control

Output

Disabled

0x00

0,0,0

ADC

Disabled

0x33

0x07

0,0,0

ADC with decimation (÷8)

256

Disabled

0x88

0xFF

0,0,0

ADC with decimation (÷256)

I/Q

0x00(5)

0x00

1,0,1

0,0,0

I/Q data

0fS/8

0x11(6)

0x00

1,1,1

0,0,0

Real without additional

decimation

8fS/8

0x44

0x0E

0x0E(7)

1,1,1

0,0,0

Real with decimation filter

(÷16)

Note 1:

When DDC is used, the actual total decimation is 2x larger since 2x is included from the DDC Half-Band Filter.

Example: Decimation = 8x with DDC-fS/2 option actually has 16x decimation with 8x provided by the decimation filter

and 2x from the DDC Half-Band Filter.

Output data and clock rate control register.

0x80<5,1,0> = <EN_NCO, EN_DDC_FS/8, EN_DDC1>.

0x81<6,3,2> = <EN_DDC2, EN_DSPP_8, 8CH_CW>.

Each of I/Q has 1/2 of fS bandwidth. The combined bandwidth is the same as the fS bandwidth. Therefore the data rate

adjustment is not needed.

The Half-Band Filter A/B includes decimation of 2.

0x0E takes into account the stages 1 and 2 are bypassed. See Figure 4-15 for “dual-channel Input” for DDC.

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