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MCP37D31-80E/TE Datasheet(PDF) 79 Page - Microchip Technology |
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MCP37D31-80E/TE Datasheet(HTML) 79 Page - Microchip Technology |
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79 / 141 page  0x66 Digital Offset Correction - Lower Byte DIG_OFFSET_GLOBAL<7:0> 0x00 0x67 Digital Offset Correction - Upper Byte DIG_OFFSET_GLOBAL<15:8> 0x00 0x68 WCK/OVR and DM1/DM2 FCB<3:0> = 0010 POL_WCK_OVR EN_WCK_OVR DM1DM2 POL_DM1DM2 0x24 0x6B PLL Calibration FCB<6:2> = 00001 PLL_CAL_TRIG FCB<1:0> = 00 0x08 0x6D PLL Output and Output Clock Phase U<1:0> EN_PLL_CLK FCB<1> = 0 DCLK_DLY_PLL<2:0> FCB<0> = 0 0x00 0x74 User-Defined Output Pattern A - Lower Byte PATTERN A<7:0> 0x00 0x75 User-Defined Output Pattern A - Upper Byte PATTERN A<15:8> 0x00 0x76 User-Defined Output Pattern B - Lower Byte PATTERN B<7:0> 0x00 0x77 User-Defined Output Pattern B - Upper Byte PATTERN B<15:8> 0x00 0x79 Dual-Channel DSPP Control EN_DSPP_2 FCB<6:0> = 000 0000 0x00 0x7A FDR and FIR_A0 FCB<5> = 0 FIR_A<0> EN_FDR FCB<4:0> = 00000 0x00 0x7B FIR A Filter FIR_A<8:1> 0x00 0x7C FIR B Filter FIR_B<7:0> 0x00 0x7D Auto-Scan Channel Order - Lower Byte CH_ORDER<7:0> 0x78 0x7E Auto-Scan Channel Order - Middle Byte CH_ORDER<15:8> 0xAC 0x7F Auto-Scan Channel Order - Upper Byte CH_ORDER<23:16> 0x8E 0x80 Digital Down-Converter Control 1 HBFILTER_B HBFILTER_A EN_NCO EN_AMPDITH EN_PHSDITH EN_LFSR EN_DDC_FS/8 EN_DDC1 0x00 0x81 Digital Down-Converter Control 2 FDR_BAND EN_DDC2 GAIN_HBF_DDC SEL_FDR EN_DSPP_8 8CH_CW GAIN_8CH<1:0> 0x00 0x82 Numerically Controlled Oscillator (NCO) Tuning - Lower Byte NCO_TUNE<7:0> 0x00 0x83 Numerically Controlled Oscillator (NCO) Tuning - Middle Lower Byte NCO_TUNE<15:8> 0x00 0x84 Numerically Controlled Oscillator (NCO) Tuning - Middle Upper Byte NCO_TUNE<23:16> 0x00 TABLE 5-3: REGISTER MAP TABLE (CONTINUED) Addr. Register Name Bits Default Value b7 b6 b5 b4 b3 b2 b1 b0 Legend: U = Unimplemented bit, read as ‘0’ FCB = Factory-Controlled Bits. Do not program 1 = bit is set 0 = bit is cleared x = bit is unknown 2: Read-only register. Preprogrammed at the factory for internal use. |
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