MCP37D31-80ESLASHTE datasheet(9/141 Pages) MICROCHIP

9 / 141 page

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DS20006382A-page 9

MCP37D31-80 AND MCP37D21-80

J10

VCMIN+

Analog Input Common-mode voltage input for auto-calibration(4)

These two pins should be tied together and connected to VCM voltage.

J11

VCMIN-

Q2/Q1-

Digital

Output

Digital data output(3)

CMOS = Q2

DDR LVDS = Q1- (Even bit first), Q9- (MSb byte first)

Serialized LVDS = Q- for channel order (n) = 7

Q3/Q1+

Digital data output(3)

CMOS = Q3

DDR LVDS = Q1+ (Even bit first), Q9+ (MSb byte first)

Serialized LVDS = Q+ for channel order (n) = 7

DM1/DM+

18-bit mode: Digital data output. DM1 and DM2 are the last two LSb bits(5)

Other modes: Not used

DCLK-

LVDS: Differential digital clock output (-)

CMOS: Not used (leave floating)

CAL

Digital

Output

Calibration status flag digital output(6)

High: Calibration is complete

Low: Calibration is not complete

GND

Supply

Common ground pin for analog and digital sections

SLAVE

Digital Input Slave or Master selection pin in AutoSync (10). If not used, tie to GND.

ADR0

SPI address selection pin (A0 bit). Tie to GND or DVDD18(7)

ADR1

SPI address selection pin (A1 bit). Tie to GND or DVDD18(7)

K10

GND

Supply

Common ground for analog and digital sections

K11

Q0/Q0-

Digital

Output

Digital data output(3)

CMOS = Q0

DDR LVDS = Q0- (Even bit first), Q8- (MSb byte first)

Serialized LVDS = Q- for the last selected channel (n=8)

Q1/Q0+

Digital data output(8)

CMOS = Q1

DDR LVDS = Q0+ (Even bit first), Q8+ (MSb byte first)

Serialized LVDS = Q+ for the last selected channel (n=8)

DM2/DM-

18-bit mode: Digital data output. DM1 and DM2 are the last two LSb bits(5)

Other modes: Not used

DCLK+

LVDS: Differential digital clock output (+)

CMOS: Digital clock output(8)

RESET

Digital Input Reset control input:

High: Normal operating mode

Low: Reset mode(9)

SYNC

Digital Input/

Output

Digital synchronization pin for AutoSync(10)

If not used, leave it floating.

GND

Supply

Common ground for analog and digital sections

CLK+

Analog Input Differential clock input (+)

CLK-

Differential clock input (-)

L10

GND

Supply

Common ground for analog and digital sections

L11

AVDD18

Analog Input Supply voltage input (1.8V) for analog section

TABLE 1-1:

PIN FUNCTION TABLE

Ball No.

Name

I/O Type

Description

MCP37D31-80E/TE Datasheet(PDF) 9 Page - Microchip Technology

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