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MCP37D31-80E/TE Datasheet(PDF) 45 Page - Microchip Technology

Part # MCP37D31-80E/TE
Description  80 Msps, 16/14-Bit High-Pr ecision Pipelined ADC
PDF  141 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP37D31-80E/TE Datasheet(HTML) 45 Page - Microchip Technology

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MCP37D31-80 AND MCP37D21-80
DS20006382A-page 45
 2020 Microchip Technology Inc.
4.7
ADC Clock Selection
This section describes the ADC clock selection and
how to use the built-in Delay-Locked Loop (DLL) and
Phase-Locked Loop (PLL) blocks.
When the device is first powered-up, the external clock
input (CLK+/-) is directly used for the ADC timing as
default. After this point, the user can enable the DLL or
PLL circuit by setting the register bits. Figure 4-11
shows the clock control blocks. Table 4-4 shows an
example of how to select the ADC clock depending on
the operating conditions.
TABLE 4-4:
ADC CLOCK SELECTION (EXAMPLE)
Operating Conditions
Control Bit Settings(1)
Features
Input Clock Duty
Cycle Correction
DCLK Output Phase
Delay Control
CLK_SOURCE = 0 (Default)(2)
• DLL output is not used
• Decimation is not used
(Default)(3)
EN_DLL = 0
EN_DLL_DCLK = 0
EN_PHDLY = 0
Not Available
Not Available
EN_DLL = 1
EN_DLL_DCLK = 0
EN_PHDLY = 0
Available
• DLL output is used
• Decimation is not used
EN_DLL = 1
EN_DLL_DCLK = 1
EN_PHDLY = 1
Available
Available
• DLL output is not used
• Decimation is used(4)
EN_DLL = 0
EN_DLL_DCLK = X
EN_PHDLY = 1
Not Available
EN_DLL = 1
EN_DLL_DCLK = 0
EN_PHDLY = 1
Available
CLK_SOURCE = 1(5)
• Decimation is not used
EN_DLL = X
EN_DLL_DCLK = X
EN_PHDLY = 0
Not Available
Available
• Decimation is used(4)
EN_DLL = X
EN_DLL_DCLK = X
EN_PHDLY = 1
Note 1:
See Addresses 0x52, 0x53, and 0x64 for bit settings.
2:
The sampling frequency (fS) of the ADC core comes directly from the input clock buffer
3:
Output data is synchronized with the output data clock (DCLK), which comes directly from the input clock buffer.
4:
While using decimation, output clock rate and phase delay are controlled by the digital clock output control block
5:
The sampling frequency (fS) is generated by the PLL circuit. The external clock input is used as the reference input
clock for the PLL block.



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