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MCP37D31-80E/TE Datasheet(PDF) 91 Page - Microchip Technology |
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MCP37D31-80E/TE Datasheet(HTML) 91 Page - Microchip Technology |
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91 / 141 page ![]() MCP37D31-80 AND MCP37D21-80 DS20006382A-page 91 2020 Microchip Technology Inc. REGISTER 5-15: ADDRESS 0X5A – PLL LOOP FILTER RESISTOR U-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 — FCB<1:0> PLL_RES<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Not used. bit 6-5 FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings. bit 4-0 PLL_RES<4:0>: Resistor value selection bits for PLL loop filter(1) 11111 = Maximum value • • • 01111= (Default) • • • 00000 = Minimum value Note 1: PLL_RES<4:0> should be set based on the phase detector comparison frequency. The resistor value increases linearly with the bit settings, from minimum to maximum values. See the PLL loop filter section in Section 4.7, "ADC Clock Selection". REGISTER 5-16: ADDRESS 0X5B – PLL LOOP FILTER CAP3 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 — FCB<1:0> PLL_CAP3<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Not used. bit 6-5 FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings. bit 4-0 PLL_CAP3<4:0>: Capacitor 3 value selection bits for PLL loop filter(1) 11111 = Maximum value • • • 00111= (Default) • • • 00000 = Minimum value Note 1: This capacitor is in series with the shunt resistor, which is set by PLL_RES<4:0>. The capacitor value increases linearly with the bit settings, from minimum to maximum values. This setting should be set based on the phase detector comparison frequency. |
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