MCP37D31-80ESLASHTE datasheet(57/141 Pages) MICROCHIP

57 / 141 page

MCP37D31-80 AND MCP37D21-80

DS20006382A-page 57

 2020 Microchip Technology Inc.

4.8.3.2

Dual-Channel DDC

Figure 4-17

shows

the

dual-channel

DDC

configuration. Each channel includes the same

processing elements as shown in the single-channel

DDC, however the I/Q outputs cannot be separately

decimated since the device only supports two

channels of decimation (four would be required for I/Q

of Channel A and I/Q of Channel B). The decimation

option can be used if the DDC output after the half-

band filter is up-converted by fS/8 for each channel.

Otherwise, I/Q of each channel will be output

separately, similar to a four-channel input device with

the WCK output pin toggling synchronously with the I-

data of Channel A. Note that the NCO phase can be

adjusted uniquely for each of the two input channels

(see Figure 4-18). Examples of setting registers for

selected output type are shown in Tables 4-16 and 4-

17.

FIGURE 4-17:

Simplified DDC Block Diagram for Dual-Channel Mode. See Tables 4-16 and 4-17 for

Using this DDC Block.

Half-Band Filter A

LP/HP

NCO (32-bit)

NCO (fS/8)

Half-Band Filter B

LP/HP

CH. B

CH. A

RealA

RealB

EN_DDC1

Down-Converting and Decimation (Note 1)

HBFILTER_B

HBFILTER_A

EN_DDC2

(Note 3)

EN_DDC_FS/8

Output Frequency Translation and Decimation (Note 1)

EN_NCO

(Note 2)

COS

ADC

Data:

SIN

COS

SIN

Note 1: See Address 0x80 – 0x81 for the Control Parameters.

2: See Figure 4-18 for details of NCO control block.

3: Half-band Filter A and B include a single-stage decimation filter.

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