MCP37D31-80ESLASHTE datasheet(70/141 Pages) MICROCHIP

70 / 141 page

 2020 Microchip Technology Inc.

DS20006382A-page 70

MCP37D31-80 AND MCP37D21-80

The output phase shift (delay) is controlled by each

unique register depending on which timing source is

used or if decimation is used. Table 4-21 shows the

output clock phase control registers for each

Configuration mode: (a) when DLL is used, (b) when

decimation is used, and (c) when PLL is used.

Figure 4-24 shows an example of the output clock

phase

delay

control

using

the

DCLK_PHD-

LY_DLL<2:0> when DLL is used.

FIGURE 4-24:

Example of Phase Shifting of Digital Output Clock (DCLK+) When DLL is Used.

TABLE 4-21:

OUTPUT CLOCK (DCLK) PHASE CONTROL PARAMETERS

Control Parameter

Operating Condition(1)

When DLL is used:

EN_PHDLY

0x64

EN_PHDLY = 1: Enable output clock phase delay control

DCLK_PHDLY_DLL<2:0>

0x52

DCLK phase delay control when DLL is used. Decimation is not used.

When decimation is used:

EN_PHDLY

0x64

EN_PHDLY = 1: Enable output clock phase delay control

DCLK_PHDLY_DEC<2:0>

DCLK phase delay control when decimation filter is used. The phase delay

is controlled in digital clock output control block.

When PLL is used:

DCLK_DLY_PLL<2:0>

0x6D

DCLK delay control when PLL is used.

Note 1:

See Figure 4-11 for details.

Output Clock

Phase Shift:

0°

45° + Default

90° + Default

135° + Default

180° + Default

225° + Default

270° + Default

315° + Default

DCLK_PHDLY_DLL<2:0>

(DCLK+)

LVDS Data Output:

Note 1: Default value may not be 0° in all operations.

(Default)(1)

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