MCP37D31-80ESLASHTE datasheet(72/141 Pages) MICROCHIP

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DS20006382A-page 72

MCP37D31-80 AND MCP37D21-80

4.12.13.1

Pseudo-random Number (PN)

Sequence Output

When TEST_PATTERNS<2:0> = 111, the device out-

puts a pseudo-random number (PN) sequence which is

defined by the polynomial of degree 16, as shown in

Equation 4-9. Figure 4-26 shows the block diagram of

a 16-bit Linear Feedback Shift Register (LFSR) for the

PN sequence.

EQUATION 4-9:

POLYNOMIAL FOR PN

• 16-Bit Mode:

The output PN[15:0] is directly applied to the output pins

Qn[15:0]. In addition to the output at the Qn[15:0] pins, the

two MSbs, PN[15] and PN[14], are copied to OVR and

WCK pins, respectively. The two LSbs, PN[1] and PN[0],

are also copied to DM1 and DM2 pins, respectively.

• 14-Bit Mode:

The output PN[15:2] is directly applied to the output

pins Qn[13:0]. In addition to the output at the Qn[13:0]

pins, the two MSbs, PN[15] and PN[14], are copied to

OVR and WCK pins, respectively.

In CMOS output mode, the pattern is always applied to

all CMOS I/O pins, regardless whether or not they are

enabled. In LVDS output mode, the pattern is only

applied to the LVDS pairs that are enabled.

FIGURE 4-26:

Block Diagram of 16-Bit LFSR

for Pseudo-Random Number (PN) Sequence for

Output Test Pattern

4.13

System Calibration

The built-in system calibration algorithm includes:

• Harmonic Distortion Correction (HDC)

• DAC Noise Cancellation (DNC)

• Dynamic Element Matching (DEM)

HDC and DNC correct the nonlinearity in the residue

amplifier

and

DAC,

respectively. The

system

calibration is performed by:

• Power-up calibration, which takes place during

the Power-on Reset sequence (requires 227 clock

cycles)

• Background calibration, which takes place during

normal operation (per 230 clock cycles).

Background calibration time is invisible to the user,

and primarily affects the ADC's ability to track

variations in ambient temperature.

The calibration status is monitored by the CAL pin or

the ADC_CAL_STAT bit in Address 0xC0 (Register 5-

79). See Address 0x07 (Register 5-5) and 0x1E

(Register 5-6) for time delay control of the auto-

calibration. Table 4-22 shows the calibration time for

various ADC core sample rates.

4.13.1

RESET COMMAND

Although the background calibration will track changes

in temperature or supply voltage, changes in clock

frequency or register configuration should be followed

by a recalibration of the ADC. This can be

accomplished via either the Hard or Soft Reset

command. The recalibration time is the same as the

power-up calibration time (227 clock cycles). Resetting

the device is highly recommended when exiting from

Shutdown or Standby mode after an extended amount

of time. During the reset, the device has the following

state:

• No ADC output

• No change in power-on condition of internal

reference

• Most of the internal clocks are not distributed

• Contents of internal user registers:

- Not affected by Soft Reset

- Reset to default values by Hardware Reset

• Current consumption of the digital section is

negligible, but no change in the analog section.



+++

Z-4

Z-9

Z-2

Z-1

XOR

PN[3]

PN[12]

PN[14]

PN[15]

TABLE 4-22:

CALIBRATION TIME VS. ADC

CORE SAMPLE RATE

fS (Msps)

Power-Up

Calibration Time1(sec)

1.5

1.7

1.9

2.2

2.7

Refresh Time (sec) of

Background Calibration2

11.9

13.4

15.3 17.9 21.5

Note 1:

It takes 227 clock cycles.

It takes place every 230 clock cycles by itself during

normal operation.

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