MCP37D31-80ESLASHTE datasheet(64/141 Pages) MICROCHIP

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DS20006382A-page 64

MCP37D31-80 AND MCP37D21-80

4.9

Digital Offset and Digital Gain

Settings

Figure 4-21 shows a simplified block diagram of the

digital offset and gain settings. Offset is applied prior to

the gain. Offset and gain adjustments occur prior to

DDC, Decimation or FDR when these features are

used.

4.9.1

DIGITAL OFFSET SETTINGS

The offset can be corrected using a 16-bit-wide global

offset correction register (0x66) for all channels, offset

correction registers for individual channels (0x9E-

0xA7) or by combining both global and individual offset

correction registers. The offset control for individual

channels can be used with DIG_OFFSET_WEIGHT

<1:0> in 0xA7. The corresponding registers for each

correction are shown in Figure 4-21.

Note that, except for the octal-channel mode, the offset

setting registers for individual channels, 0x9E-0xA7

(Registers 5-70 – 5-78),

not

sequentially

correspond to the channel order defined by

CH_ORDER<23:0>. Table 4-18 shows the details of

the offset registers that correspond to the actual

channels, depending on the number of channels used.

4.9.2

DIGITAL GAIN SETTINGS

CH(N)_DIG_GAIN<7:0> in Addresses 0x96 – 0x9D

(Registers 5-62 – 5-69) is used to adjust the digital gain

per channel.

FIGURE 4-21:

Simplified Block Diagram for Digital Offset and Gain Settings.

Note 1: Digital Offset Setting: Register mapping

(0x9E – 0xA7) to the corresponding

channel is not sequential to the channel

order defined by CH_ORDER<23:0>,

except for the octal-channel mode. See

Table 4-18 for details.

2: Gain and NCO Phase Offset: Register

mapping to the corresponding channel is

sequential to the channel order defined

by CH_ORDER<23:0>.

TABLE 4-18:

1st Channel 2nd Channel 3rd Channel

4th Channel

5th Channel 6th Channel 7th Channel 8th Channel

10x9F

─

0xA0

0x9F

─

0xA1

0x9F

0xA0

─

0xA2

0x9F

0xA0

0xA1

─

0xA3

0x9F

0xA0

0xA1

0xA2

─

0xA4

0x9F

0xA0

0xA1

0xA2

0xA3

─

0xA5

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

─

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

CH(n)_DIG_GAIN<7:0>

Digital Offset Control

ADC

Digital Gain Control

Output

Corrected

ADC Output

CH(n)_DIG_OFFSET<7:0>

DIG_OFFSET_WEIGHT<1:0>

Global Digital Offset Control

DIG_OFFSET_GLOBAL<15:0>

for individual channel

(See Address 0x66)

(See Addresses 0x9E – 0xA5)

(See Address 0xA7)

(See Addresses 0x96 – 0x9D)

for all channels

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