MCP37D31-80ESLASHTE datasheet(73/141 Pages) MICROCHIP

73 / 141 page

MCP37D31-80 AND MCP37D21-80

DS20006382A-page 73

 2020 Microchip Technology Inc.

4.13.1.1

Hardware Reset

A hard reset is triggered by toggling the RESET pin. On

the rising edge, all internal calibration registers and

user registers are initialized to their default states and

recalibration of the ADC begins. The recalibration time

is the same as the power-up calibration time. See

Figure 2-8 for the timing details of the hardware

RESET pin.

4.13.1.2

Soft Reset

The user can issue a Soft Reset command for a fast

recalibration of the ADC by setting the SOFT_RESET

bit to ‘0’ in Address 0x00 (Register 5-1). During Soft

Reset, all internal calibration registers are initialized to

their initial default states. User registers are unaffected.

When exiting the Soft Reset (changing from ‘0’ to ‘1’),

an automatic device calibration takes place.

4.14

Power Dissipation and Power

Savings

The power dissipation of the ADC core is proportional

to the sample rate (fS). The digital power dissipation of

the CMOS outputs are determined primarily by the

strength of the digital drivers and the load condition on

each output pin. The maximum digital load current

(ILOAD) can be calculated as:

EQUATION 4-10:

CMOS OUTPUT LOAD

CURRENT

The capacitive load presented at the output pins needs

to be minimized to minimize digital power consumption.

The output load current of the LVDS output is constant,

since it is set by LVDS_IMODE<2:0> in Address 0x63

(Register 5-21).

4.14.1

POWER-SAVING MODES

This device has two power-saving modes:

• Shutdown

• Standby

They are set by the SHUTDOWN and STANDBY bits in

Address 0x00 (Register 5-1).

In Shutdown mode, most of the internal circuitry,

including the reference and clock, are turned off with

the exception of the SPI interface. During Shutdown,

the device consumes 23 mA (typical), primarily due to

digital leakage. When exiting from Shutdown, issuing a

Soft Reset at the same time is highly recommended.

This will perform a fast recalibration of the ADC. The

contents of the internal registers are not affected by the

Soft Reset.

In Standby mode, most of the internal circuitry is

disabled except for the reference, clock and SPI

interface. If the device has been in standby for an

extended period of time, the current calibration value

may not be accurate. Therefore, when exiting from

Standby mode, executing the device Soft Reset at the

same time is highly recommended.

4.15

AutoSync Mode: Synchronizing

Multiple ADCs at the same Clock

using Master and Slave

Configuration

AutoSync allows multiple devices to sample analog

inputs synchronously at the same clock edge. Output

data is also presented synchronously if they are using

the same digital post-processing options. Figure 4-27

shows the system configuration using the AutoSync

feature. Three examples with timing diagram are

shown in Figure 2-9

– Figure 2-11.

Once the devices are synchronized, each device

performs internal calibration (

TPCAL) before sending out

valid data output. Any ADC data output before the

calibration is complete should be ignored.

Note that the calibration time varies slightly from device

to device, and the internal calibration status can be

monitored using the CAL pin or ADC_CAL_STAT bit in

the Register Address 0xC0.

The valid synchronized output is available when all

devices complete their own internal calibration. For

this reason, the user has two options for the

synchronized output: (a) monitor the calibration status

of individual devices and wait until all devices

complete calibrations or (b) use an external AND gate

as shown in Figure 4-26. Master and all Slave devices

are synchronized when the AND gate output toggles

to “High”.

The AutoSync feature can be used with the following

steps:

• Master device is selected by setting SLAVE pin to

“GND”: SYNC pin becomes output pin.

• Slave device is selected by setting SLAVE pin to

“High” (or tie to DVDD): SYNC pin becomes input

pin.

• Feed the Master’s SYNC pin output to Slave’s

SYNC pin.

• Use AutoSync mode using (a) Power-On Reset

(Figure 2-9), (b) RESET Pin (Figure 2-10), or (c)

SOFT RESET bit (Figure 2-11).

ILOAD

DVDD1.8 fDCLK NCLOAD



Where:

N = Number of bits

CLOAD = Capacitive load of output pin

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