JS48F4400P0P3C0 datasheet(128/139 Pages) NUMONYX

128 / 139 page

Numonyx™ StrataFlash® Cellular Memory (M18)

Datasheet

April 2008

128

309823-10

new command is issued to the chip at that Partition Address. This allows the user to set partition #1's output state to Read

Array, and partition #4's output state to Read Status. Each time the partition address is changed to partition #4 (without

issuing a new command), the Status will be read from the chip.

Illegal commands include commands outside of the allowed command set (allowed commands: 41H [pgm], 20H [erase],

etc.)

All partitions default to Read Array on powerup.

If a Read Array is attempted from a busy partition, the result is unreliable data. When the user returns to this partition

address later, the output mux will be in the “Read Array” state from its last visit. the Read ID and Read Query commands

perform the same function in the device. The ID and Query data are located at different locations in the address map.

1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will

occur.

The Clear Status command clears only the error bits in the status register if the device is not in the following modes: 1)

WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes) 2) Suspend states (Erase

Suspend, Pgm Suspend, Pgm Suspend In Erase Suspend).

BEFP writes are allowed only when the status register bit #0 = 0 or else the data is ignored.

The current state is that of the chip and not of the partition. Each partition remembers which output (Array, ID/CFI or

Status) it was last pointed to on the last instruction to the chip, but the next state of the chip does not depend on where

the partition's output mux is presently pointing to.

Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register and Blank Check) perform the

operation and then move to the Ready State.

10.

Buffered programming will botch when a different block address (as compared to address given with E9 command) is

written during the BP Load1 and BP Load2 states.

11.

WA0 refers to the block address latched during the first write cycle of the current operation.

12.

All two cycle commands are considered as a contiguous whole during device suspend states. Individual commands are not

parsed separately; that is, the 2nd cycle of an erase command issued in program suspend will NOT resume the program

operation.

13.

The Buffered Program setup command (0xE9) will not change the partition state. The Buffered Program Confirm command

(0xD0) will place the partition in read status mode.

Appendix A AADM Mode

A.1

AADM Feature Overview

The following is a list of general requirements for AADM mode. Additional details can be

found in subsequent sections.

• Feature Availability: AADM mode is available in devices that are configured as A/

D MUX. With this configuration, AADM mode is enabled by setting a specific volatile

bit in the RCR.

• High Address Caputure (A[MAX:16]): When AADM mode is enabled,

A[MAX:16] and A[15:0] are captured from the A/DQ[15:0] balls. The selection of

A[MAX:16] or A[15:0] is determined by the state of the OE# input, as A[MAX:16]

is captured when OE# is at VIL.

• Read & Write Cycle Support: In AADM mode, both asynchronous and

synchronous Cycles are supported.

• Customer Requirements: For AADM operation, the customer is required to

ground A16-Amax.

• Other Characteristics: For AADM, all other device characteristics (pgm time,

erase time, ICCS, etc.) are the same as A/D MUX unless otherwise stated.

A.2

AADM Mode Enable (RCR[4]=1)

Setting RCR.4 to its non-default state (‘1b) enables AADM mode:

• The default device configuration upon Reset or Powerup is A/D MUX Mode

• Upon setting RCR[4]=1, the upper Addresses A[max:16] are latched as all 0’s by

default.

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