JS48F4400P0P3C0 datasheet(133/139 Pages) NUMONYX

133 / 139 page

April 2008

Datasheet

309823-10

133

Numonyx™ StrataFlash® Cellular Memory (M18)

A.3.3

Synchronous Read and Write Cycles

Just as asynchronous bus cycles, synchronous bus cycles (RCR[15] = ‘0b) can have

one or two address cycles. If the are two address cycles, the upper address must be

latched first with OE# at VIL followed by the lower address with OE# at VIH. If there is

only one address cycle, only the lower address will be latched and the previously

latched upper address applies. For reads, sensing begins when the lower address is

latched, but for synchronous reads, addresses are latched on a rising clock CLK instead

of a rising ADV# edge.

For synchronous bus cycles with two address cycles, it is not necessary to de-assert

ADV# between the two address cycles. This allows both the upper and lower address to

be latched in only two clock periods.

A.3.3.1

Synchronous Read Cycles

For synchronous read specifications, refer to Table 65, “AADM Synchronous Timings” on

page 133. For synchronous read timing diagrams, refer to the following:

• Figure 65, “AADM Sync Burst Read Cycle (ADV# De-asserted between Address

Cycles)” on page 134

• Figure 66, “AADM Sync Burst Read Cycle (ADV# Not De-asserted between Address

Cycles)” on page 134

• Figure 67, “AADM Sync Burst Read Cycle (Latching A[15:0] only)” on page 135

Notes:

The device must operate down to 9.6MHz in synchronous burst mode.

During the address capture phase of a read burst bus cycle, OE# timings relative to CLK shall be identical to those of

ADV# relative to CLK.

In synchronous burst read cycles, the asynchronous OE# to ADV# setup and hold times must also be met (Tghvh & Tvhgl)

to signify that the address capture phase of the bus cycle is complete.

To prevent A/D bus contention between the host and the memory device, OE# may only be asserted low after the host has

satisfied the ADDR hold spec, Tchax.

Rise and fall time specified between Vil & Vih

A read cycle may only be terminated (prior to the completion of sensing data) one time before a full bus cycle must be

allowed to complete.

Table 65: AADM Synchronous Timings

Num

Sym

Target (104 MHz)

(108MHz)

Notes

(3)

Num

Sym

Target (104 MHz)

(108MHz)

Notes

(3)

Min (nS)

Max (nS)

Min (nS)

Max (nS)

R201

tCLK

See note

R311

tCHVL

2.5

R203

tRISE/FALL

1.5

R312

tCHTX

R301

tAVCH

R313

tCHVH

R302

tVLCH

R314

tCHGL

2.5

R303

tELCH

3.5

R316

tVLVH

tCLK

2*tCLK

R304

tCHQV

R317

tVHCH

R305

tCHQX

R318

tCHGH

R306

tCHAX

R319

tGHCH

R307

tCHTV

R320

tGLCH

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