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JS48F4400P0P3C0 Datasheet(PDF) 136 Page - Numonyx B.V

Part # JS48F4400P0P3C0
Description  StrataFlash짰 Cellular Memory
PDF  139 Pages
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

JS48F4400P0P3C0 Datasheet(HTML) 136 Page - Numonyx B.V

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Numonyx™ StrataFlash® Cellular Memory (M18)
Datasheet
April 2008
136
309823-10
Appendix B Additional Information
Appendix C Ordering Information
To order samples, obtain datasheets or inquire about any stack combination, please
contact your local Numonyx representative.
Order Number
Document/Tool
315567
Numonyx™ StrataFlash® Cellular Memory (M18) Developer’s Manual
307654
Numonyx™ StrataFlash® Cellular Memory (M18 SCSP); 2048-Mbit M18 (Non-Mux and AD-Mux I/O)
Family with Synchronous PSRAM Datasheet
310048
Designing with Numonyx™ StrataFlash® Wireless Memory and Pre-enabling Numonyx™ StrataFlash®
Cellular Memory, Application Note 822
309311
Numonyx™ StrataFlash® Cellular Memory (M18 SCSP) to ARM® PrimeCellTM Design Guide, Application
Note 841
315651
Migration Guide for Numonyx™ StrataFlash® Cellular Memory (M18) 90 nm to 65 nm, Application Note
860
310058
Effect of Program Buffer Size on System Interrupt Latency, Application Note 816
Notes:
4.
Visit Numonyx’s World Wide Web home page at http://www.numonyx.com for technical documentation and tools or for
the most current information on Numonyx flash products.
Table 66: 38F Type Stacked Components
PF
38F
5070
M0
Y
0
B
0
Package
Designator
Product Line
Designator
Product Die/
Density
Configuration
NOR Flash Prodcut
Family
Voltage/NOR
Flash CE#
Configuration
Parameter /
Mux
Configuration
Ballout
Identifier
Device
Details
PF =
SCSP, RoHS
RD =
SCSP, Leaded
Stacked NOR
Flash + RAM
Char 1 = Flash
die #1
Char 2 = Flash
die #2
Char 3 =
RAM die #1
Char 4 =
RAM die #2
(See
Table 68,
“38F / 48F
Density
Decoder”
on
page 137 for
details)
First character
applies to Flash
die #1
Second character
applies to Flash
die #2
(See
Table 69,
“NOR Flash
Family
Decoder” on
page 138 for
details)
V =
1.8 V Core
and I/O;
Separate Chip
Enable per die
(See
Table 70,
“Voltage /
NOR Flash
CE#
Configurati
on
Decoder”
on
page 138
for details)
0 =
No parameter
blocks; Non-
Mux I/O
interface
(See
Table 71,
“Parameter
/ Mux
Configurati
on
Decoder”
on
page 138
for details)
B =
x16D
Ballout
(See
Table 72
,
“Ballout
Decoder
” on
page 13
9 for
details)
0 =
Original
released
version of
this
product



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