DP83266 datasheet(110/152 Pages) NSC

110 / 152 page

70 Control Information (Continued)

Indicate Mode Configuration Register (IMCR)

The Indicate Mode Configuration Register (IMCR) defines configuration options for all three indicate Channels including the sort

mode frame filtering and status breakpoints

This register may be written only when the INSTOP bit in the State Attention Register is set It may be written with its current

value any time which is useful for one-shot sampling

This register is not altered upon reset

Access Rules

Address

Read

Write

117h

Always

INSTOP Mode Only

SM1

SM0

SKIP

FPP

BOT2

BOT1

BOB

BOS

Bit

Symbol

Description

BOS

Breakpoint on Service Opportunity

Enables the end of a service opportunity to generate an Indicate

breakpoint attention (ie set the Channel’s BRK bit in the Indicate Attention Register) Service opportunities

include receipt of a Token a MAC Frame or a ring operational change following some copied frames This bit

should be set to 1 if BRKI0 will be used

BOB

Breakpoint on Burst

Enables the end of a burst to generate an Indicate breakpoint attention (ie set the

Channel’s BRK bit in the Indicate Attention Register) End of burst includes Channel change DA change SA

change or MAC INFO change A Channel change is detected from the FC field of valid copied frames A DA

change is detected when a frame’s DA field changes from this station’s address to any other An SA change is

detected when a frame’s SA field is not the same as the previous one A MAC INFO change occurs when a

MAC frame does not have the identical first four bytes of INFO as the previous frame This breakpoint always

sets the BRK bit (ie this breakpoint is always enabled)

BOT1

Breakpoint on Threshold for ICHN1

Enables the value in the Indicate Threshold Register to be used to

generate an Indicate breakpoint attention on Indicate Channel 1 (ie set the BRK1 bit in the Indicate Attention

BOT2

Breakpoint on Threshold for ICHN2

Enables the value in the Indicate Threshold Register to be used to

generate an Indicate breakpoint attention on Indicate Channel 2 (ie set the BRK2 bit in the Indicate Attention

FPP

Frame-per-Page

This bit controls how received frames are packed into the Pool Space Pages which are

provided via the PSP Descriptors When this bit is reset the MACSI device assembles multiple frames into a

single page of Pool Space when possible (ie the frames are smaller than the 4 kByte page size) When this

bit is set the MACSI device will force a page break and fetch a new PSP for each frame received This

guarantees that no page will contain more than one frame When FPP is set Frame packing can be re-enabled

on individual channels See ‘‘Address Configuration Register (ACR)’’

This mode is useful for systems where received frames are not processed in order of receipt This is because

space reclamation is greatly simplified A side affect of this mode is that no frame will span more than two

pages (ie a frame will have at most two IDUDs)

SKIP

Skip Enable

Enables filtering on Indicate Channel 0 when the Copy Control field for ICHN0 in the Indicate

Configuration Register is set to 01 or 10 When this bit is set only the unique MAC frames received on Indicate

Channel 0 will be copied to memory (ie those having an FC field or first four bytes of the Information field that

differs from the previous frame) When this bit is 0 the MACSI will copy all MAC frames that meet the Copy

Criteria When this bit changes froma0toa1 the MACSI will copy the next MAC frame even if it is the same

as the previous frame Note that the ‘‘Promiscuous’’ Copy Mode overrides this SKIP mode (when the User

selects Promiscuous copy and the SKIP mode the MACSI will copy all MAC frames)

110

DP83266 Datasheet(PDF) 110 Page - National Semiconductor (TI)

DP83266 Datasheet(HTML) 110 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL