DP83266 datasheet(117/152 Pages) NSC

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70 Control Information (Continued)

712 POINTER RAM REGISTER DESCRIPTIONS

The Pointer RAM Register set contains 32 28-bit registers

Registers 23 through 31 are reserved and user access of

these locations produces undefined results Pointer RAM

Registers are read and written by the host using the Pointer

RAM Operation (PTOP) service function and are accessed

directly by MACSI device hardware during Indicate and Re-

quest operations After initialization the Pointer RAM Regis-

ters are maintained by the MACSI device and do not require

host intervention

During Indicate and Request operations Pointer RAM regis-

ters are used as addresses for ABus accesses of data and

Descriptors

the subchannel addresses for loads

(reads) of streams of PSPs ODUs ODUDs and REQs and

for stores (writes) of streams of IDUs IDUDs and CNFs

Pointer RAM Registers include the following

ODU Pointer

Contains the address of an Output Data Unit

During Request operations this register is loaded by the

MACSI device from the Location Field of its Output Data

Unit Descriptor

ODUD List Pointer

Loaded by the MACSI device from the

Location Field of the REQ Descriptor when it is read from

memory The address is incremented by the MACSI device

as each ODUD is fetched from memory

CNF Queue Pointer

Contains the current CNF Status

Queue address This register is written by the user after he

has allocated space for the CNF Queue During Request

operations this register is incremented by the MACSI de-

vice after each CNF is written to the CNF Queue

REQ Queue Pointer

Initialized by the host with the start

address of the REQ Descriptor Queue after the Queue has

been initialized During Request operations the address is

incremented by the MACSI device as each REQ is fetched

IDU Pointer

Written by the MACSI device with the Location

Field of the PSP Descriptor when it is loaded from the PSP

pre-fetch register

IDUD Queue Pointer

Points to the Queue location where

IDUDs will be stored Written by the user after he has allo-

cated space for the IDUD Status Queue Incremented by

the MACSI device as IDUDs are written to consecutive loca-

tions in the Queue

PSP Queue Pointer Register

Points to the next available

PSP Initialized by the host with the start address of the PSP

Queue As each PSP is read from memory this register is

incremented

Next PSP Register

Written by the MACSI device with the

PSP fetched from the PSP Queue

Indicate Shadow Register

Written by the MACSI device

with the start address of the last IDU copied to memory

Request Shadow Register

Written by the MACSI device

with the address of the current ODUD

See

Figure 7-3 for Summary including address and access

rules

713 LIMIT RAM REGISTER DESCRIPTIONS

The Limit RAM Register set contains 16 9-bit registers

Registers 11 through 15 are reserved and access of these

locations produces undefined results

The Limit RAM registers contain data values that define the

limits of each of the ten queues maintained by the MACSI

device

Limit RAM Registers are read and written by the host using

the Limit RAM Operation (LMOP) service function when the

StatusSpace Machine is in STOP Mode and are read di-

rectly by MACSI device hardware during Indicate and Re-

quest operations

Limit RAM Registers include the following

REQ Queue Limit

Defines the last valid REQ written by the

host

CNF Queue Limit Register

Defines the last Queue loca-

tion where a CNF may be written by the MACSI device Due

to pipelining the MACSI device may write up to two CNFs

after it detects a write to the next-to-last CNF entry (and

generates a No Status Space Attention) For this reason

the host must always define the CNF queue limit to be one

Descriptor less than the available space

IDUD Queue Limit Register

Defines the last Queue loca-

tion where an IDUD may be written by the MACSI device

PSP Queue Limit

Defines the last valid PSP written by the

host

See

Figure 7-4 for Summary including address and access

rules

117

DP83266 Datasheet(PDF) 117 Page - National Semiconductor (TI)

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