DP83266 datasheet(136/152 Pages) NSC

136 / 152 page

80 Signal Descriptions (Continued)

85 ABus INTERFACE

The ABus interface signals provide a 28-bit address 32-bit data bus for transfers between the host system and the MACSI

device The ABus uses a bus requestbus grant protocol that allows for multiple bus masters supports burst transfers of 4 or 8

32-bit words and permits both physical and virtual addressing using fixed-size pages

Address and Data

Symbol

Description

BP3 – 0

50 61 72 83

ABus Byte Parity

These TRI-STATE signals contain the parity for each address

and data byte of AB

AD such that AB

BP0 is the parity for AB

AD7-0 AB

BP1

is the parity for AB

AD15-8 etc

AD31 – 0

40 – 42 45 – 49

ABus Address and Data

These TRI-STATE signals are the multiplexed ABus

51 – 53 56 – 60

address and data lines During the address phase of a cycle AB

AD27-0 contain

62 – 65 68 – 71

the 28-bit address When SIMR1EAM e 1 AB

AD31-28 contain a value specified

73 – 76 79 – 82

by the user (by programming SIMR1AB

A31 – 27) during the address cycle When

SIMR1EAM e 0 AB

AD31-28 contain a 4-bit function code identifying the type of

transaction encoded as follows

AD 3128

Transaction Type

RCHN1 ODU Load

RCHN1 ODUD LoadCNF Store

RCHN1 REQ Load

RCHN0 ODU Load

RCHN0 ODUD LoadCNF Store

RCHN0 REQ Load

ICHN2 IDU Store

ICHN2 IDUD Store

ICHN2 PSP Load

ICHN1 IDU Store

ICHN1 IDUD Store

ICHN1 PSP Load

ICHN0 IDU Store

ICHN0 IDUD Store

ICHN0 PSP Load

PTR RAM LoadStore

A27–2

25–19 16–5

ABus Demultiplexed Address

These TRI-STATE signals contain the word

2 – 1 160 – 156

address during ABus accesses They are driven from Tpa to the last Td state

negated in the following Tr state then released Note that the timing of these signals

is under software control via the System Interface Mode Register 1 (SIMR1) For

MACSI revision A through C the User must set SIMR1ATM to one for the

demultiplexed address pins AB

A (272) to work properly For MACSI revision D

and later (SI revision t 0x00000058) the User may use the demultiplexed address

pins AB

A (272) with SIMR1ATM set to one or zero Since the MACSI device

makes only word (4 byte) accesses on the ABus the device does not include pins

for AB

A (10) These pins would drive a zero for every access

136

DP83266 Datasheet(PDF) 136 Page - National Semiconductor (TI)

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