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DP83266 Datasheet(PDF) 138 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 138 Page - National Semiconductor (TI) |
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138 / 152 page ![]() 80 Signal Descriptions (Continued) 86 ELECTRICAL INTERFACE Symbol Pin IO Description LBC5 3 125 126 I Local Byte Clock 125 MHz clocks with a 5050 duty-cycle generated by the PLAYERa device LBC1 127 I Local Byte Clock 125 MHz clock with a 5050 duty-cycle generated by the PLAYERa LSC 124 I Local Symbol Clock 25 MHz clock with a 4060 duty-cycle generated by the PLAYERa device RST 128 I Reset Active Low input which resets the Internal State Machines and most Registers This signal must be asserted for at least five clock cycles When asserted all bidirectional signals are at TRI-STATE TCK 95 I TCK JTAG Scan Clock TMS 94 I TMS JTAG Mode Select TDI 93 I TDI JTAG Data In TDO 92 O TDO JTAG Data Out TRST 91 I TRST JTAG Reset Active low signal VCC 11 3 17 32 Positive Power Supply 5V 10% relative to GND 43 54 66 77 97 113 135 146 GND 11 4 18 33 Ground Power Supply Return 44 55 67 78 96 112 134 145 RSRVD0 88 I Reserved 0 Must be connected to ground 100 101 NC 89 No Connect Must be left unconnected 138 |
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