BLUENRG-1 datasheet(65/173 Pages) STMICROELECTRONICS

65 / 173 page

BlueNRG-1

Functional details

DocID028866 Rev 1

65/173

When the RTS flow control is enabled, the UART_RTS signal is asserted until the receive

FIFO is filled up to the programmed watermark level. When the CTS flow control is

enabled, the transmitter can only transmit data when the UART_CTS signal is asserted.

Table 67: Control bits to enable and disable hardware flow control

CTSEN

RTSEN

Function

Both RTS and CTS flow control disabled.

Only RTS flow control enabled.

Only CTS flow control enabled.

Both RTS and CTS flow control enabled.

The RTS flow control logic is linked to the programmable receive FIFO watermark levels.

When RTS flow control is enabled, the UART_RTS is asserted until the receive FIFO is

filled up to the watermark level. When the receive FIFO watermark level is reached, the

UART_RTS signal is de-asserted, indicating that there is no more room to receive any

more data. The transmission of data is expected to cease after the current character has

been transmitted. The UART_RTS signal is reasserted when data has been read out of the

receive FIFO so that it is filled to less than the watermark level. If RTS flow control is

disabled and the UART is still enabled, then data is received until the receive FIFO is full,

or no more data is transmitted to it.

If CTS flow control is enabled, then the transmitter checks the UART_CTS signal before

transmitting the next byte. If the UART_CTS signal is asserted, it transmits the byte

otherwise, transmission does not occur. The data continues to be transmitted while

UART_CTS is asserted, and the transmit FIFO is not empty. If the transmit FIFO is empty

and the UART_CTS signal is asserted no data is transmitted. If the UART_CTS signal is

de-asserted and CTS flow control is enabled, then the current character transmission is

completed before stopping. If CTS flow control is disabled and the UART is enabled, then

the data continues to be transmitted until the transmit FIFO is empty.

3.9.2.4

Software flow control

Software flow control is enabled through register UART_XFCR bit SFEN.

Software receive flow control

Once the software receive flow control is enabled, the receiver compares the incoming data

with the programmed Xoff values. Different combinations of software receive flow control,

which can be selected through SFRMOD, where only 1 character match is needed or in

which 2 Xoff characters must be received sequentially.

Table 68: Control bits to enable and program receive software flow control

SFSEN

SFRMOD

Function

xxb

Software flow control disabled.

00b

Software receive flow control disabled.

01b

Use Xon1, Xoff1 for matching.

10b

Use Xon2, Xoff2 for matching.

11b

Use Xon1 & Xon2, Xoff1 & Xoff2 for matching.

If received characters match the programmed Xoff values, the transmission will stop as

soon as the current character is completely transferred. The interrupt bit XOFFRIS in the

raw interrupt register UART_RIS is set. If the corresponding interrupt mask bit is set, the

BLUENRG-1 Datasheet(PDF) 65 Page - STMicroelectronics

BLUENRG-1 Datasheet(HTML) 65 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL