BLUENRG-1 datasheet(49/173 Pages) STMICROELECTRONICS

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BlueNRG-1

Functional details

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Table 42: DMA_CHx - CNDTR register description: address offset

DMA_CHX_BASE_ADDR+0x04

Bit

Field name

Reset

Description

15:0

NDT

0x0

Number of data to be transferred (0 up to 65535). This register

can only be written when the channel is disabled. Once the

channel is enabled, this register is read-only, indicating the

remaining bytes to be transmitted. This register decrements

after each DMA transfer. Once the transfer is completed, this

the value previously programmed if the channel is configured

in auto-reload mode. If this register is zero, no transaction can

be served whether the channel is enabled or not.

31:16

RESERVED

0x0

RESERVED

Table 43: DMA_CHx - CPAR register description: address offset

DMA_CHX_BASE_ADDR+0x08

Bit

Field

name

Reset

Description

31:0

0x0

Base address of the peripheral data register from/to which the data

will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is

ignored. Access is automatically aligned to a halfword address.

When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is

automatically aligned to a word address.

Table 44: DMA_CHx - CMAR register description: address offset

DMA_CHX_BASE_ADDR+0x0C

Bit

Field

name

Reset

Description

31:0

0x0

Base address of the memory area from/to which the data will be

read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored.

Access is automatically aligned to a halfword address. When MSIZE

is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to

a word address.

3.8

SPI

3.8.1

Introduction

The BlueNRG-1 integrates a serial peripheral interface compatible with Motorola standard.

Main features are:



Maximal supported baud rate is 1 MHz in slave mode and 8 MHz in master mode.



Parallel-to-serial conversion on data written to an internal 32-bit wide, 16-location

deep transmitter FIFO.



Serial-to-parallel conversion on received data, buffering in a 32-bit wide 16-location

deep receive FIFO.



Programmable data frame size from 4-bit to 32-bit.



Programmable clock bit rate and prescaler.



Programmable clock phase and polarity in SPI mode.



Support for Direct Memory Access (DMA).

BLUENRG-1 Datasheet(PDF) 49 Page - STMicroelectronics

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