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BLUENRG-1 Datasheet(PDF) 30 Page - STMicroelectronics |
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BLUENRG-1 Datasheet(HTML) 30 Page - STMicroelectronics |
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30 / 173 page  Functional details BlueNRG-1 30/173 DocID028866 Rev 1 3.6.3 ADC registers ADC peripheral base address (ADC_BASE_ADDR) 0x40800000. Table 25: ADC registers Address offset Name RW Reset Description 0x00 CTRL RW 0x00000000 ADC control register. Refer to the detailed description below. 0x04 CONF RW 0xFFFFFFFF ADC configuration register. Refer to the detailed description below. 0x08 IRQSTAT R 0x00000000 IRQ masked status register. Refer to the detailed description below. 0x0C IRQMASK RW 0x0000000F It sets the mask for ADC interrupt. Refer to the detailed description below. 0x14 DATA_CONV R 0x00000000 Result of the conversion in two complement format: if ROUND16 = 0: result is mapped on all 32-bit (can be truncated with loss of DATAOUT[30:15]) if ROUND16 = 1: result is mapped on 16-bit (can be truncated with loss of DATAOUT[15:0]) 0x18 OFFSET RW 0x00000000 Offset for correction of converted data 0x20 SR_REG RW 0x00000000 ADC status register. Refer to the detailed description below. 0x24 THRESHOLD_HI RW 0xFFFFFFFF High threshold for window comparator 0x28 THRESHOLD_LO RW 0x00000000 Low threshold for window comparator Table 26: ADC - CTRL register description: address offset ADC_BASE_ADDR+0x00 Bit Field name Reset RW Description 0 ON 0x0 RW Starts ADC analog subsystem. This bit must be set before starting a conversion. 0: ADC is OFF. 1: ADC is ON. 1 CALEN 0x0 RW Enables the calibration phase when set to 1. This bit is cleared and the calibration is disabled by setting the RSTCALEN bit. 2 SWSTART 0x0 RW Starts the ADC conversion phase when set. 3 RESET 0x0 RW Reset all the ADC registers when set. = 4.36 ∗ ( 1 − 0.622) + 2.7 |
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