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BLUENRG-1 Datasheet(PDF) 33 Page - STMicroelectronics |
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BLUENRG-1 Datasheet(HTML) 33 Page - STMicroelectronics |
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33 / 173 page  BlueNRG-1 Functional details DocID028866 Rev 1 33/173 Bit Field name Reset RW Description 31:4 RESERVED 0x0 R RESERVED Table 29: ADC - IRQMASK register description: address offset ADC_BASE_ADDR+0x0C Bit Field name Reset RW Description 0 ENDCAL 0x1 RW Interrupt mask for the end of calibration event: 0: Interrupt is enabled. 1: Interrupt is disabled. 1 BUSY 0x1 RW Interrupt mask for the ADC busy event: 0: Interrupt is enabled. 1: Interrupt is disabled. 2 EOC 0x1 RW Interrupt mask for the end of conversion event: 0: Interrupt is enabled. 1: Interrupt is disabled. 3 WDOG 0x1 RW Interrupt mask for the within the threshold event: 0: Interrupt is enabled. 1: Interrupt is disabled. 31:4 RESERVED 0x0 R RESERVED Table 30: ADC - DATA_CONV register description: address offset ADC_BASE_ADDR+0x14 Bit Field name Reset RW Description 31:0 DATA_CONV 0x00000000 R Result of the conversion in two complement format: If ROUND16 = 0: result is mapped on all 32-bit (can be truncated with loss of DATA_CONV[30:15]). If ROUND16 = 1: result is mapped on 16-bit (can be truncated with loss of DATA_CONV [15:0]). Table 31: ADC - OFFSET register description: address offset ADC_BASE_ADDR+0x18 Bit Field name Reset RW Description 31:0 OFFSET 0x00000000 RW Offset for correction of converted data. Table 32: ADC - SR_REG register description: address offset ADC_BASE_ADDR+0x20 Bit Field name Reset RW Description 0 ENDCAL 0x0 RW 1: when the calibration is completed. The result of the calibration is written in the OFFSET register. 1 BUSY 0x0 RW 1: during conversion. 2 EOC 0x0 RW 1: when the conversion is completed. 3 WDOG 0x0 RW If ENAB_COMP = 1, this bit indicates the result of the conversion is between high and low threshold: 0: DATAOUT[31:0] is NOT between THRESHOLD_HI and THRESHOLD_LO values. 1: DATAOUT[31:0] is between THRESHOLD_HI and THRESHOLD_LO values. 31:4 RESERVED 0x0 R RESERVED |
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