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BLUENRG-1 Datasheet(PDF) 75 Page - STMicroelectronics |
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BLUENRG-1 Datasheet(HTML) 75 Page - STMicroelectronics |
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75 / 173 page ![]() BlueNRG-1 Functional details DocID028866 Rev 1 75/173 Table 79: UART - CR register description: address offset UART_BASE_ADDR+0x30 Bit Field name Reset RW Description 0 EN 0x0 RW UART enable. This bit enables the UART. 0: UART is disabled. 1: UART is enabled. Data transmission and reception can occur. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 2:1 RESERVED 0x0 R RESERVED 3 OVSFACT 0x0 RW UART oversampling factor.This bit enables the UART oversampling factor. If UARTCLK is 16 MHz thus max. baud-rate is 1 Mbaud when OVSFACT = 0b, and 2 Mbaud when OVSFACT = 1b. 0: UART it is 16 UARTCLK clock cycles. 1: UART it is 8 UARTCLK clock cycles. 7:4 RESERVED 0x0 R RESERVED 8 TXE 0x1 RW Transmit enable. 0b: UART TX disabled. 1b: UART TX enabled. 9 RXE 0x1 RW Receive enable. 0b: UART RX disabled. 1b: UART RX enabled. 10 RESERVED 0x0 R RESERVED 11 RTS 0x0 RW Request to send. 0: RTS is high. 1: RTS is low. 13:12 RESERVED 0x0 R RESERVED 14 RTSEN 0x0 RW RTS hardware flow control enable. 0b: RTS disabled. 1b: RTS enabled. Data is only requested when there is space in the receive FIFO for it to be received. 15 CTSEN 0x0 RW CTS hardware flow control enable. 0b: CTS disabled. 1b: CTS enabled. Data is only transmitted when the CTS is asserted. 19:16 STA_B_DURATION 0x4 RW START bit duration Receiver state. These bits can be used to configure the START bit duration (in clock cycles) to get the bit sampled in the middle of the UART receiver. These bits can be used only when using high baud rates (IBRD = 1, FBRD >= 0 and OVSFACT = 1). Below the formula to calculate the START bit duration receiver state: STA_B_DURATION = Integer(Fuartclk/(2* BAUD RATE)) - 1 Example: when UARTCLK = 16 MHz and BAUD RATE = 2.0 Mbps then STA_B_DURATION = 4 - 1 = 3. STA_B_DURATION field should be configured with 4'b0011. |
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