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BLUENRG-1 Datasheet(PDF) 28 Page - STMicroelectronics |
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BLUENRG-1 Datasheet(HTML) 28 Page - STMicroelectronics |
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28 / 173 page ![]() Functional details BlueNRG-1 28/173 DocID028866 Rev 1 The conversion can be single (CONT = 0) or continuous (CONT = 1). In continuous mode, the conversion runs with a preprogrammed sampling rate, while in single step mode the ADC performs a conversion and then stops. The output data rate depends on DECIM_RATE according to the table below. Table 23: ADC data rate DECIM_RATE Output data rate [Ksample/s] 0 (200) 5 1 (100) 10 2 (64) 15.625 3 (32) 31.25 The system can work in conjunction with an external MEMS microphone by setting MIC_SEL. In this mode, an IO configured as PDM_CLK provides the clock to the external microphone, while an IO configured as PDM_DATA received the PDM stream from the external microphone. The external clock is 1.6 MHz (DIG_FILT_CLK = 0) or 0.8 MHz (DIG_FILT_CLK = 1). The output data rate changes with DECIM_RATE according to Table 24: "ADC data rate with microphone mode". Table 24: ADC data rate with microphone mode DIG_FILT_CLK DECIM_RATE Output data rate [Ksample/s] 1 (clock = 0.8 MHz) 0 (200) 4 1 (100) 8 2 (64) 12.5 3 (32) 25 0 (clock = 1.6 MHz) 0 (200) 8 1 (100) 16 2 (64) 25 3 (32) 50 3.6.2.1 ADC start conversion The ADC both analog and digital sub-system are switched on by setting ADCON and SWSTART. The conversion operation consists of four phases. 1. The wake-up phase lasts 5 us, is present at the beginning of a single acquisition, with the goal to let the analog system to settle before to start the acquisition. 2. If the CALEN is set, a calibration phase is performed. It permits to compensate the offset in the analog part. The conversion status is tracked by SR status register. At the beginning of the conversion the BUSY bit is set and masks any attempt to change CONF, up to the end of the conversion. At end of this conversion, the ENDCAL flag is generated and the OFFSET register is written with the converted offset voltage. 3. The acquisition phase is regulated by a timeout depending on the resolution. In this phase, digital filter chain processes the data coming from ADC. |
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