BLUENRG-1 datasheet(86/173 Pages) STMICROELECTRONICS

86 / 173 page

Functional details

BlueNRG-1

86/173

DocID028866 Rev 1

Bit

Field name

Reset

Description

5:4

0x0

Speed mode. SM defines the speed mode related to the

serial bit rate:

0: Standard mode (up to 100 K/s).

1: Fast mode (up to 400 K/s).

SGCM

0x0

Slave general call mode defines the operating mode of the

slave controller when a general call is received. This setting

does not affect the hardware general call that is always

managed in transparent mode.

0: transparent mode, the slave receiver recognizes the

general call but any action is taken by the hardware after the

decoding of the message included in the Rx FIFO.

1: direct mode, the slave receiver recognizes the general call

and executes directly (without software intervention) the

related actions. Only the status code word is stored in the

I2C_SR register for notification to the application.

FTX

0x0

FTX flushes the transmit circuitry (FIFO, fsm). The

configuration of the I2C node (register setting) is not affected

by the flushing operation. The flushing operation is

performed on modules working on different clock domains

(system and I2C clocks) and needs several system clock

cycles before being completed. Upon completion, the I2C

node (internal logic) clears this bit. The application must not

access the Tx FIFO during the flushing operation and should

poll on this bit waiting for completion.

0: Flush operation is completed (I2C controller clears the bit).

1: Flush operation is started and in progress (set by

application).

FRX

0x0

FRX flushes the receive circuitry (FIFO, fsm).The

configuration of the I2C node (register setting) is not affected

by the flushing operation. The flushing operation is

performed on modules working on different clock domains

(system and I2C clocks) and needs several system clock

cycles before to be completed. Upon completion, the I2C

node (internal logic) clears this bit. The application must not

access the Rx FIFO during the flushing operation and should

poll on this bit waiting for the completion.

0: Flush operation is completed (I2C controller clears the bit).

1: Flush operation is started and in progress (set by

application).

DMA_TX_EN

0x0

Enables the DMA TX interface.

0: Idle state, the DMA TX interface is disabled.

1: Run state, the DMA TX interface is enabled.

On the completion of the DMA transfer, the DMA TX

interface is automatically turned off clearing this bit when the

end of transfer signal coming from the DMA is raised.

DMA_TX_EN and DMA_RX_EN must not enabled at the

same time.

BLUENRG-1 Datasheet(PDF) 86 Page - STMicroelectronics

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