BLUENRG-1 datasheet(68/173 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-1

68/173

DocID028866 Rev 1

3.9.2.9

Transmit interrupt

The transmit interrupt is asserted HIGH when one of the following conditions occurs:



If the FIFOs are enabled and the number of characters in the transmit FIFO is less

than the programmed watermark level. It is cleared by performing writes to the

transmit FIFO until it holds more characters than the programmed watermark level, or

by clearing the interrupt by software.



If the FIFOs are disabled (have a depth of one location) and there is no data present

in the transmitter single location. It is cleared by performing a single write to the

transmit FIFO, or by clearing the interrupt by software.

The transmit FIFO service interrupt is based on a transition through a level, rather

than on the level itself. When the interrupt and the UART are enabled before any

data is written to the transmit FIFO, the interrupt is not set. The interrupt is only

set once written data leaves the single location of the transmit FIFO and it

becomes empty.

When the TX FIFO is disabled, the DATA can be written on the bottom of the

FIFO during the transmission of a previous DATA, or in another words, when the

holding register is busy.

The interrupt is de-asserted when we write the next DATA on the bottom of the TX

FIFO. If we write DATA only on the holding register and the bottom of the TX

FIFO is empty, the only way to clear the interrupt is by the software.

3.9.2.10

Timeout interrupt

The receive timeout interrupt is asserted when the receive FIFO is not empty, and no

further data is received (or no correct start bit of a frame is detected in the RX line) over a

programmable timeout period. This mechanism ensures that the user is aware that data is

still present in the receive FIFO and requires servicing. The receive timeout interrupt is

cleared either when the FIFO becomes empty through reading all the data (or by reading

the holding register), or when a 1b is written to the corresponding bit of the UART_ICR

3.9.2.11

Error interrupt

The error interrupt is asserted when an error occurs in the reception of data by the UART.

The interrupt can be caused by the following error conditions:



Framing



Parity



Break



Overrun.

The cause of the interrupt is available by reading the UART_RIS or UART_MIS registers.

The interrupt can be cleared by writing to the relevant bits of the UART_ICR register.

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