BLUENRG-1 datasheet(97/173 Pages) STMICROELECTRONICS

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BlueNRG-1

Functional details

DocID028866 Rev 1

97/173

Bit

Field name

Reset

Description

BERR

0x0

Bus Error. BERR is set when an unexpected Start/Stop

condition occurs during a transaction. The related actions are

different, depending on the type of operation in progress.The

status code word in the SR contains a specific error tag

(CAUSE field) for this error condition. This interrupt is cleared

by setting the related bit of the ICR register.

0: No bus error detection.

1: Bus error detection.

27:26

RESERVED

0x0

RESERVED

MTDWS

0x0

Master transaction done without stop. MTDWS is set when a

master operation (write or read) has been executed and a stop

(MCR:P field) is not programmed. The application shall read

the related transaction status (SR register), the pending data

in the RX FIFO (only for a master read operation) and clear

this interrupt (transaction acknowledgment). A subsequent

master operation can be issued (by writing the MCR register)

after clearing this interrupt. A subsequent slave operation will

be notified (RISR:WTSR and RISR:RFSR interrupt bits

assertion) after clearing this interrupt, meanwhile the I2C clock

line will be stretched low. This interrupt is cleared by setting

the related bit of the ICR register:

0: Master transaction acknowledged.

1: Master transaction done (ready for acknowledgment) and

stop is not applied into the I2C bus.

31:29

RESERVED

0x0

RESERVED

Table 104: I2C - MISR register description: address offset I2CX_BASE_ADDR+0x34

Bit

Field name

Reset

Description

TXFEMIS

0x0

TX FIFO empty masked interrupt status.

0: TX FIFO is not empty.

1: TX FIFO is empty.

TXFNEMIS

0x0

TX FIFO nearly empty masked interrupt status.

0: Number of entries in TX FIFO greater than the

TFTR:THRESHOLD_TX register.

1: Number of entries in TX FIFO less than or equal to the

TFTR:THRESHOLD_TX register.

TXFFMIS

0x0

Tx FIFO full masked interrupt status.

0: TX FIFO is not full.

1: TX FIFO is full.

TXFOVRMIS

0x0

Tx FIFO overrun masked interrupt status.

0: No overrun condition occurred in TX FIFO.

1: Overrun condition occurred in TX FIFO.

RXFEMIS

0x0

RX FIFO empty masked interrupt status.

0: RX FIFO is not empty.

1: RX FIFO is empty.

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