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BLUENRG-1 Datasheet(PDF) 47 Page - STMicroelectronics |
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BLUENRG-1 Datasheet(HTML) 47 Page - STMicroelectronics |
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47 / 173 page  BlueNRG-1 Functional details DocID028866 Rev 1 47/173 Bit Field name Reset RW Description 24 CGIF6 0x0 W Channel 6 global interrupt flag. This bit is set by software. 0: No effect. 1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register. 25 CTCIF6 0x0 W Channel 6 transfer complete flag. This bit is set by software. 0: No effect. 1: Clears the corresponding TCIF flag in the ISR register. 26 CHTIF6 0x0 W Channel 6 half transfer flag. This bit is set by software. 0: No effect. 1: Clears the corresponding HTIF flag in the ISR register. 27 CTEIF6 0x0 W Channel 6 transfer error flag. This bit is set by software. 0: No effect. 1: Clears the corresponding TEIF flag in the ISR register. 28 CGIF7 0x0 W Channel 7 global interrupt flag. This bit is set by software. 0: No effect. 1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register. 29 CTCIF7 0x0 W Channel 7 transfer complete flag. This bit is set by software. 0: No effect. 1: Clears the corresponding TCIF flag in the ISR register. 30 CHTIF7 0x0 W Channel 7 half transfer flag. This bit is set by software. 0: No effect. 1: Clears the corresponding HTIF flag in the ISR register. 31 CTEIF7 0x0 W Channel 7 transfer error flag. This bit is set by software. 0: No effect. 1: Clears the corresponding TEIF flag in the ISR register. DMA_CH0 peripheral base address (DMA_CH0_BASE_ADDR) 0xA0000008 DMA_CH1 peripheral base address (DMA_CH1_BASE_ADDR) 0xA000001C DMA_CH2 peripheral base address (DMA_CH2_BASE_ADDR) 0xA0000030 DMA_CH3 peripheral base address (DMA_CH3_BASE_ADDR) 0xA0000044 DMA_CH4 peripheral base address (DMA_CH4_BASE_ADDR) 0xA0000058 DMA_CH5 peripheral base address (DMA_CH5_BASE_ADDR) 0xA000006C DMA_CH6 peripheral base address (DMA_CH6_BASE_ADDR) 0xA0000080 DMA_CH7 peripheral base address (DMA_CH7_BASE_ADDR) 0xA0000094 Table 40: DMA_CHx registers Address offset Name RW Reset Description 0x00 CCR RW 0x00000000 DMA channel configuration register. Refer to the detailed description below. 0x04 CNDTR RW 0x00000000 DMA channel number of data register. Refer to the detailed description below. 0x08 CPAR RW 0x00000000 DMA channel peripheral address register. Refer to the detailed description below. 0x0C CMAR RW 0x00000000 DMA channel memory address register. Refer to the detailed description below. |
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