BLUENRG-1 datasheet(95/173 Pages) STMICROELECTRONICS

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BlueNRG-1

Functional details

DocID028866 Rev 1

95/173

Bit

Field name

Reset

Description

LBR

0x0

Length number of bytes received. LBR is set in case of MR or

WTS and when the number of bytes received is equal to the

transaction length programmed in the MCR:LENGTH (master

mode) or SMB_SCR:LENGTH (slave mode). On the assertion

of this interrupt and when the bit CR:FRC_STRTCH is set, the

hardware starts clock stretching, the CPU shall download the

data byte (Command code, Byte Count, Data...) from RX

FIFO, re-set the expected length of the transaction in

SMB_SCR:LENGTH and clear the interrupt. When clearing

this interrupt the hardware continues the transfer. This

interrupt is cleared by setting the related bit of the ICR

0: Length number of bytes is not received.

1: Length number of bytes is received.

RFSR

0x0

Read-from-slave request. RFSR is set when a read-from-slave

"Slavetransmitter" request is received (I2C slave is addressed)

from the I2C line. On the assertion of this interrupt the TX

FIFO is flushed (pending data are cleared) and the CPU shall

put the data in TX FIFO. This bit is self-cleared by writing data

in FIFO. In case the FIFO is empty before the completion of

the read operation, the RISR:RFSE interrupt bit is set.This

interrupt is cleared by setting the related bit of the ICR

0: Read-from-slave request has been served.

1: Read-from-slave request is pending.

RFSE

0x0

Read-from-slave empty. RFSE is set when a read-from-slave

operation is in progress and TX FIFO is empty. On the

assertion of this interrupt, the CPU shall download in TX FIFO

the data required for the slave operation. This bit is self-

cleared by writing in TX FIFO. At the end of the read-from-

slave operation this bit is cleared although the TX FIFO is

empty.

0: TX FIFO is not empty.

1: TX FIFO is empty with the read-from-slave operation in

progress.

WTSR

0x0

Write-to-slave request. WTSR is set when a write-to-slave

operation is received (I2C slave is addressed) from the I2C

line. This notification can be used by the application to

program the DMA descriptor when required. This interrupt is

cleared by setting the related bit of the ICR register:

0: No write-to-slave request pending.

1: Write-to-slave request is pending.

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