BLUENRG-1 datasheet(87/173 Pages) STMICROELECTRONICS

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BlueNRG-1

Functional details

DocID028866 Rev 1

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Bit

Field name

Reset

Description

DMA_RX_EN

0x0

Enables the DMA RX interface.

0: Idle state, the DMA RX interface is disabled.

1: Run state, the DMA RX interface is enabled.

On the completion of the DMA transfer, the DMA RX

interface is automatically turned off clearing this bit when the

end of transfer signal coming from the DMA is raised.

DMA_TX_EN and DMA_RX_EN must not enabled at the

same time.

14:12

RESERVED

0x0

RESERVED

14:13

FON

0x0

Filtering on sets the digital filters on the SDA, SCL line,

according to the I2C bus requirements, when standard open-

drain pads are used:

00b: No digital filters are inserted.

01b: Digital filters (filter 1 ck wide spikes) are inserted.

10b: Digital filters (filter 2 ck wide spikes) are inserted.

11b: Digital filters (filter 4 ck wide spikes) are inserted.

FS_1

0x0

Force stop enable bit. When set to 1b, the STOP condition is

generated.

0: Force stop disabled.

1: Enable force stop.

31:16

RESERVED

0x0

RESERVED

Table 93: I2C - SCR register description: address offset I2CX_BASE_ADDR+0x04

Bit

Field name

Reset

Description

6:0

SA7

0x55

Slave address 7-bit. SA7 includes the slave address 7-bit or

the LSB bits of the slave address 10-bit

9:7

ESA10

0x0

Extended slave address 10-bit. ESA10 includes the extension

(MSB bits) to the SA7 register field in case of slave addressing

mode set to 10-bit

21:15

RESERVED

0x0

RESERVED

31:16

SLSU

0xF

Slave data setup time. SLSU defines the data setup time after

SCL clock stretching in terms of i2c_clk cycles. Data setup

time is actually equal to SLSU-1 clock cycles. The typical

values for i2c_clk of 16 MHz are SLSU = 5 in standard mode

and SLSU = 3 in fast modes.

Table 94: I2C2 - MCR register description: address offset I2CX_BASE_ADDR+0x0C

Bit

Field name

Reset

Description

0x0

Operation

0: Indicates a master write operation.

1: Indicates a master read operation.

7:1

0x0

Address. Includes the 7-bit address or the LSB bits of the10-

bit address used to initiate the current transaction

10:8

EA10

0x0

Extended address. Includes the extension (MSB bits) of the

field A7 used to initiate the current transaction

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