BLUENRG-1 datasheet(74/173 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-1

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Table 78: UART - LCRH_TX register description: address offset UART_BASE_ADDR+0x2C

Bit

Field name

Reset

Description

BRK

0x0

Send break. This bit allows a continuous low-level to be forced

on TX output, after completion of the current character. This bit

must be asserted for at least one complete frame transmission

time in order to generate a break condition. The transmit FIFO

contents remain unaffected during a break condition.

0: Normal transmission.

1: Break condition transmission.

PEN_TX

0x0

TX parity enable:

0: Parity disabled.

1: Parity Enable.

EPS_TX

0x0

TX even parity select. This bit selects the parity generation,

when the parity is enabled (PEN_TX =1b). This bit has no effect

when parity is disabled (PEN_TX = 0b).

0: Odd parity generation and checking is performed during

transmission, which check for an odd number of 1s in data and

parity bits.

1: Even parity generation and checking is performed during

transmission, which check for an even number of 1s in data and

parity bits.

STP2_TX

0x0

TX two stop bits select. This bit enables the check for two stop

bits being received:

0: 1 stop bit received.

1: 2 stop bits received.

FEN_TX

0x0

TX Enable FIFO. This bit enables/disables the transmit TX

FIFO buffer:

0: TX FIFO is disabled (character mode), i.e. the TX FIFO

becomes a 1-byte deep holding register.

1: TX FIFO is enabled.

6:5

WLEN_TX

0x0

TX word length. This bit field indicates the number of data bits

transmitted in a frame as follows:

00b: 5 bits.

01b: 6 bits.

10b: 7 bits.

11b: 8 bits.

SPS_TX

0x0

TX Stick parity check:

0: stick parity disable.

1: when PEN_TX = 1b (parity enabled) and EPS_TX = 1b (even

parity), the parity is transmitted as a 0. When PEN_TX = 1b and

EPS_TX = 0b (odd parity), the parity bit is transmitted as a 1.

31:8

RESERVED

0x0

RESERVED

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