S32K311NHT0MPAST datasheet(128/143 Pages) NXP

128 / 143 page

Rev 8, Jun 2023

• In section " LPSPI" updated symbols of Data hold time (inputs) to tHI.

• Updated heading of Ethernet MII and RMII to mention support of 10 and 100 Mbps.

• In "uSDHC SDR electrical specifications" updated conditions for the supported pads.

• In "uSDHC DDR electrical specifications" updated conditions for the supported pads and deleted 25 MHz specifications.

• Updated RϴJA for 172HDQFP_EP to 15.6 °C/W.

Rev 7, Apr 2023

• Updated caution in overview and updated feature comparison.

• In "S32K3xx chip's feature comparison" section clarified via footnote that S32K388 supports QuadSPI SDR modes only.

• Updated S32K312 and S32K388 block diagram.

• QFP package references updated to HDQFP.

• In section "Absolute maximum ratings" added footnote to VDD_DCDC as "Voltage at VDD_DCDC cannot be higher than

VDD_HV_A".

• In section "Voltage and current operating requirements" added footnote to V15 as "Min and Max values are applicable

only for non-SMPS mode where V15 is sourced externally".

• Updated descriptions and condition in following sections:

— Boot time, HSE firmware not installed

— Boot time, HSE firmware installed

— HSE firmware memory verification time examples

• In section "Recommended Decoupling Capacitors" updated variants for COUT V11.

• In section "V15 regulator (SMPS option) electrical specifications" added CBULK_SMPS.

• In section "V15 regulator (BJT option, NPN ballast transistor control) electrical specifications" added V15 input.

• In section "SAR ADC" updated paragraph "All below specs are applicable...". and added footnote to TUE as "Spec valid

if potential difference between VDD_HV_A.." and figure updated to show VDD_HV_A instead of VREFH.

• In LPCMP section changed ACMP0 to LPCMP0.

• In PLL added paragraph to mention Auxiliary PLL applicability and footnote updated to mention "Accumulated jitter

specification is not valid with SSCG".

• In PLL added CLKIN_VIL_EXTAL_BYPASS and CLKIN_VIH_EXTAL_BYPASS specifications.

• Added section "Communication between two S32K388 devices".

• In section "Ethernet MII (100 Mbps)" updated specification for 10 and 100 Mbps.

• In section "Ethernet RGMII" added paragraph "The following timing specs are defined at the device".

• In section "MDIO timing specifications" updated MDC3 for GPIO[113]pad of S32K388.

• Added following QuadSPI modes for S32K388:

— QuadSPI Quad 3.3V SDR 103.33MHz

— QuadSPI Quad 3.3V SDR 125MHz

• In QuadSPI modes, mentioned the applicability to the devices in K3 family.

NXP Semiconductors

Revision history

S32K3xx Data Sheet, Rev. 9.1, 03/2024

Data Sheet: Technical Data

Preliminary Information for S32K388

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S32K311NHT0MPAST Datasheet(PDF) 128 Page - NXP Semiconductors

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