S32K311NHT0MPAST datasheet(126/143 Pages) NXP

126 / 143 page

Rev 9, January 2024

— For "tWPSCK", removed "high or low" from description.

— Updated information "All measurements are with maximum output load of 30pf.." at the top of the table.

— Removed Rise/Fall time output specs.

— Added footnotes "Output rise/fall time is determined by the output load and GPIO pad drive strength setting..." and

"The input rise/fall time specification applies to both clock and data..."

— Added "tV" and "tHO" spec with condition "Master Loopback, S32K388 LPSPI2 and LPSPI5 @20MHz"

— For "tV" with max value "17.5" ns, updated condition to ""Master Loopback, applies to all devices LPSPI0 @20 MHz"

— For "tHO" with min value "-2" ns, updated condition to ""Master Loopback, applies to all devices LPSPI0 @20 MHz"

— Updated LPSPI timing diagrams with 50/50 levels.

• In "LPSPI" and "Timing specification for S32K388 to S32K388", updated information from "All timing is shown

with respect to 20% VDD_HV_A/B and 80% VDD_HV_A/B thresholds" to "All timing is shown with respect to 50%

VDD_HV_A/B thresholds."

• Added information "Valid pin combinations to be referred from K3xx*_Use sheet in IOmux." in all SAI, uSHDC, QSPI and

Ethernet modes.

• Added information "Data transitions measured at 30%/70% supply for the write path. Data transitions measured at

mid-supply for the read path. Clock transitions measured at mid-supply." in all QSPI modes.

• Changed footer to "Preliminary Information for S32K388"

• Updated Preliminary Information for S32K388 throughout the data sheet.

• In "HSE Firmware memory verification time examples" table, there are some TBC's. Those will be updated in the next

revision as new measurements showed different timings. There is no major performance degradation to be expected.

• Added information in section "LPSPI 20 MHz and 15MHz combinations", and removed S32K344 PAD TYPE column from

Table. "LPSPI 20 MHz and 15MHz combinations".

• Added new section "LPSPI2 and LPSPI5 20MHz combination for S32K388".

• In "Timing specification for S32K388 to S32K388", updated maximum output load from 30pF to 50pF.

• In "Ethernet RGMII", updated footnote to "Output timing valid for maximum external load CL = 13.5 pF (includes PCB trace,

package trace (around 2pF) and flash input load)...."

• In "QuadSPI Octal 3.3V DDR 120MHz", for spec "fSCK_DQS", updated condition from "DLL and Auto-Learning mode

enabled" to "DLL enabled"

• In section "uSDHC SDR electrical specifications":

— Updated description for "fpp" spec.

— Updated condition for "tOD" with description "SDHC Output delay(Output valid)"

— Added 2 rows of spec "tOD" with value "-5.6" and description ""fpp= 25 MHz, 400 KHz,..." and "fpp= 50 MHz, SDHC_

CLK to SDHC_CMD".

— Updated min value for spec "tIH" to 2 ns.

— Removed footnote " In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7V to 3.6V."

• In '"uSDHC" modes :

Table continues on the next page...

NXP Semiconductors

Revision history

S32K3xx Data Sheet, Rev. 9.1, 03/2024

Data Sheet: Technical Data

Preliminary Information for S32K388

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