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MCP37D31-80E/TE Datasheet(PDF) 111 Page - Microchip Technology |
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MCP37D31-80E/TE Datasheet(HTML) 111 Page - Microchip Technology |
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111 / 141 page  MCP37D31-80 AND MCP37D21-80 DS20006382A-page 111 2020 Microchip Technology Inc. REGISTER 5-56: ADDRESS 0X90 – CH5 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH5_NCO_PHASE<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CH5_NCO_PHASE<7:0>: Lower byte of CH5_NCO_PHASE<15:0>(1) 1111-1111 = 1.4° when CH5_NCO_PHASE<15:0> = 0x00FF • • • 0000-0000 = 0° when CH5_NCO_PHASE<15:0> = 0x0000 (Default) Note 1: See Note 1 - Note 3 in Register 5-46. CH5 is the 6th channel selected by CH_ORDER<23:0> bits. REGISTER 5-57: ADDRESS 0X91 – CH5 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH5_NCO_PHASE<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CH5_NCO_PHASE <15:8>: Upper byte of CH5_NCO_PHASE<15:0>(1) 1111-1111 = 359.995° when CH5_NCO_PHASE<15:0> = 0xFFFF • • • 0000-0000 = 0° when CH5_NCO_PHASE<15:0> = 0x0000 (Default) Note 1: See Note 1 - Note 3 in Register 5-46. CH5 is the 6th channel selected by CH_ORDER<23:0> bits. REGISTER 5-58: ADDRESS 0X92 – CH6 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH6_NCO_PHASE<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CH6_NCO_PHASE<7:0>: Lower byte of CH6_NCO_PHASE<15:0>(1) 1111-1111 = 1.4° when CH6_NCO_PHASE<15:0> = 0x00FF • • • 0000-0000 = 0° when CH6_NCO_PHASE<15:0> = 0x0000 (Default) Note 1: See Note 1 - Note 3 in Register 5-46. CH6 is the 7th channel selected by CH_ORDER<23:0> bits. |
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