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MCP37D31-80E/TE Datasheet(PDF) 108 Page - Microchip Technology |
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MCP37D31-80E/TE Datasheet(HTML) 108 Page - Microchip Technology |
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108 / 141 page  2020 Microchip Technology Inc. DS20006382A-page 108 MCP37D31-80 AND MCP37D21-80 REGISTER 5-47: ADDRESS 0X87: CH0 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0_NCO_PHASE<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CH0_NCO_PHASE<15:8>: Upper byte of CH0_NCO_PHASE<15:0>(1) 1111-1111 = 359.995° when CH0_NCO_PHASE<15:0> = 0xFFFF • • • 0000-0000 = 0° when CH0_NCO_PHASE<15:0> = 0x0000 (Default) Note 1: See Note 1 - Note 3 in Register 5-46. REGISTER 5-48: ADDRESS 0X88 – CH1 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH1_NCO_PHASE<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CH1_NCO_PHASE<7:0>: Lower byte of CH1_NCO_PHASE<15:0>(1) 1111-1111 = 1.4° when CH1_NCO_PHASE<15:0> = 0x00FF • • • 0000-0000 = 0° when CH1_NCO_PHASE<15:0> = 0x0000 (Default) Note 1: See Note 1 - Note 3 in Register 5-46. CH1 is the 2nd channel selected by CH_ORDER<23:0> bits. REGISTER 5-49: ADDRESS 0X89 – CH1 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH1_NCO_PHASE<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CH1_NCO_PHASE <15:8>: Upper byte of CH1_NCO_PHASE<15:0>(1) 1111-1111 = 359.995° when CH1_NCO_PHASE<15:0> = 0xFFFF • • • 0000-0000 = 0° when CH1_NCO_PHASE<15:0> = 0x0000 (Default) Note 1: See Note 1 - Note 3 in Register 5-46. CH1 is the 2nd channel selected by CH_ORDER<23:0> bits. |
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