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MCP37D31-80E/TE Datasheet(PDF) 104 Page - Microchip Technology |
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MCP37D31-80E/TE Datasheet(HTML) 104 Page - Microchip Technology |
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104 / 141 page  2020 Microchip Technology Inc. DS20006382A-page 104 MCP37D31-80 AND MCP37D21-80 REGISTER 5-39: ADDRESS 0X7F – AUTO-SCAN CHANNEL ORDER (UPPER BYTE) R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 CH_ORDER<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CH_ORDER<23:16>: Upper byte of CH_ORDER<31:0>(1) 1000-1110 = Default Note 1: See Table 5-3 for the channel order selection. See SEL_NCH<2:0> in Address 0x01 (Register 5-2) for the number of channels to be selected. REGISTER 5-40: ADDRESS 0X80 – DIGITAL DOWN-CONVETER CONTROL 1(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HBFILTER_B HBFILTER_A EN_NCO EN_AMPDITH EN_PHSDITH EN_LFSR EN_DDC_FS/8 EN_DDC1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 HBFILTER_B: Select half-bandwidth filter at DDC output of channel B in dual-channel mode(2) 1 = Select High-Pass filter at DDC output 0 = Select Low-Pass filter at DDC output (Default) bit 6 HBFILTER_A: Select half-bandwidth filter at DDC output of channel A(2) 1 = Select High-Pass filter at DDC output 0 = Select Low-Pass filter at DDC output (Default) bit 5 EN_NCO: Enable NCO of DDC1 1 = Enabled 0 = Disabled (Default) bit 4 EN_AMPDITH: Enable amplitude dithering for NCO(3, 4) 1 = Enabled 0 = Disabled (Default) bit 3 EN_PHSDITH: Enable phase dithering for NCO(3, 4) 1 = Enabled 0 = Disabled (Default) bit 2 EN_LFSR: Enable linear feedback shift register (LFSR) for amplitude and phase dithering for NCO 1 = Enabled 0 = Disabled (Default) bit 1 EN_DDC_FS/8: Enable NCO for the DDC2 to center the DDC output signal to be around fS/8/DER(5) 1 = Enabled 0 = Disabled (Default) bit 0 EN_DDC1: Enable digital down converter 1 (DDC1) 1 = Enabled(6) 0 = Disabled (Default) Note 1: This register is used for single-, dual- and octal-channel modes when CW feature is enabled (8CH_CW = 1). 2: This filter includes a decimation of 2. -Single-channel mode: HBFILTER_A is used. -Dual-channel mode: Both HBFILTER_A and HBFILTER_B are used. 3: This requires the LFSR to be enabled: EN_LFSR=1 4: EN_AMPDITH = 1 and EN_PHSDITH = 1 are recommended for the best performance. 5: DER is the decimation rate defined by FIR A or FIR B filter. If up-converter is not enabled (disabled), output is I/Q data. 6: DDC and NCO are enabled. For DDC function, bits 0, 2 and 5 need to be enabled all together. |
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