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MCP37D31-80E/TE Datasheet(PDF) 101 Page - Microchip Technology |
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MCP37D31-80E/TE Datasheet(HTML) 101 Page - Microchip Technology |
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101 / 141 page  MCP37D31-80 AND MCP37D21-80 DS20006382A-page 101 2020 Microchip Technology Inc. REGISTER 5-33: ADDRESS 0X79 – DUAL-CHANNEL DIGITAL SIGNAL POST-PROCESSING CONTROL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EN_DSPP_2 FCB<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EN_DSPP_2: Enable all digital post-processing functions for dual-channel operations 1 = Enabled 0 = Disabled (Default) bit 6-0 FCB<6:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings. REGISTER 5-34: ADDRESS 0X7A – FRACTIONAL DELAY RECOVERY AND FIR_A0(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FCB<5> FIR_A<0> EN_FDR FCB<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 FCB<5>: Factory-Controlled Bit. This is not for the user. Do not change default setting. bit 6 FIR_A<0>: Enable the first 2x decimation (Stage 1A in FIR A) in single-channel mode(2) 1 = Enabled 0 = Disabled (Default) bit 5 EN_FDR: Enable fractional delay recovery (FDR) option 1 = Enabled (with delay of 59 clock cycles). 0 = Disabled (Default) bit 4-0 FCB<4:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings. Note 1: This register is used only for single and dual-channel modes. 2: This is the LSb for the FIR A filter settings. For the first 2x decimation, set FIR_A<0> = 1 for single-channel operation, and FIR_A<0> = 0 for dual-channel operation. See Address 0x7B (Register 5-35) for FIR_A<8:1> settings. |
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