| Electronic Components Datasheet Search |
|
MCP37D31-80E/TE Datasheet(PDF) 102 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
MCP37D31-80E/TE Datasheet(HTML) 102 Page - Microchip Technology |
|
102 / 141 page ![]() 2020 Microchip Technology Inc. DS20006382A-page 102 MCP37D31-80 AND MCP37D21-80 REGISTER 5-35: ADDRESS 0X7B – FIR A FILTER(1,5) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIR_A<8:1> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 FIR_A<8:1>: Decimation Filter FIR A settings for Channel A (or I)(2) Single-Channel Mode:(3) FIR_A<8:0> = 1-1111-1111 = Stage 1 - 9 filters (decimation rate: 512) 0-1111-1111 = Stage 1 - 8 filters 0-0111-1111 = Stage 1 - 7 filters 0-0011-1111 = Stage 1 - 6 filters 0-0001-1111 = Stage 1 - 5 filters 0-0000-1111 = Stage 1 - 4 filters 0-0000-0111 = Stage 1 - 3 filters (decimation rate = 8) 0-0000-0011 = Stage 1 - 2 filters (decimation rate = 4) 0-0000-0001 = Stage 1 filter (decimation rate = 2) 0-0000-0000 = Disabled all FIR A filters. (Default) Dual-Channel Mode:(4) FIR_A<8:0> = 1-1111-1110 = Stage 2 - 9 filters (decimation rate: 256) 0-1111-1110 = Stage 2 - 8 filters 0-0111-1110 = Stage 2 - 7 filters 0-0011-1110 = Stage 2 - 6 filters 0-0001-1110 = Stage 2 - 5 filters 0-0000-1110 = Stage 2 - 4 filters 0-0000-0110 = Stage 2 - 3 filters 0-0000-0010 = Stage 2 filter (decimation rate = 2) 0-0000-0000 = Disabled all FIR A filters. (Default) Note 1: This register is used only for single and dual-channel modes. The register values are thermometer encoded. 2: FIR_A<0> is placed in Address 0x7A (Register 5-34). 3: In single-channel mode, the 1st stage filter is selected by FIR_A<0> = 1 in Address 0x7A (Register 5-34). 4: In dual-channel mode, the 1st stage filter is disabled by setting FIR_A<0> = 0 in Address 0x7A. 5: SNR is improved by approximately 2.5 dB per each filter stage, and output data rate is reduced by a factor of two per stage. The data and clock rates in Address 0X02 (Register 5-3) need to be updated accordingly. Address 0x64 (Register 5-22) setting is also affected. The maximum decimation rate for the single-channel mode is 512, and 256 for the dual-channel mode. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |