MCP37D31-80ESLASHTE datasheet(103/141 Pages) MICROCHIP

103 / 141 page

MCP37D31-80 AND MCP37D21-80

DS20006382A-page 103

 2020 Microchip Technology Inc.

ADDRESS 0X7C – FIR B FILTER(1,2)

R/W-0

FIR_B<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

FIR_B<7:0>:Decimation Filter FIR B settings for Channel B (or Q)(3)

1111-1111 = Stage 2 - 9 filters (decimation rate = 256)

0111-1111 = Stage 2 - 8 filters

0011-1111 = Stage 2 - 7 filters

0001-1111 = Stage 2 - 6 filters

0000-1111 = Stage 2 - 5 filters

0000-0111 = Stage 2 - 4 filters

0000-0011 = Stage 2 - 3 filters

0000-0001 = Stage 2 filter (decimation rate = 2)

0000-0000 = Disabled all FIR B Filters. (Default)

Note

This register is used for the dual-channel mode only. The register values are thermometer encoded.

EN_DSPP_2 bit in Address 0x79 (Register 5-34) must be set when using decimation in dual-channel mode.

SNR is improved by approximately 2.5 dB per each filter stage, and output data rate is reduced by a factor of two per stage. The

data and clock rates in Address 0X02 (Register 5-3) need to be updated accordingly. Address 0x64 (Register 5-22) setting is

also affected. The maximum decimation factor for the dual-channel mode is 256.

ADDRESS 0X7D – AUTO-SCAN CHANNEL ORDER (LOWER BYTE)

R/W-0

R/W-1

R/W-0

CH_ORDER<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

CH_ORDER<7:0>: Lower byte of CH_ORDER<31:0>(1)

0111-1000 = Default

Note

See Table 5-3 for the channel order selection. See SEL_NCH<2:0> in Address 0x01 (Register 5-2) for the number of channels

to be selected.

ADDRESS 0X7E – AUTO-SCAN CHANNEL ORDER (MIDDLE BYTE)

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

CH_ORDER<15:8>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

CH_ORDER<15:8>: Middle byte of CH_ORDER<31:0>(1)

1010-1100 = Default

Note

See Table 5-3 for the channel order selection. See SEL_NCH<2:0> in Address 0x01 (Register 5-2) for the number of channels

to be selected.

MCP37D31-80E/TE Datasheet(PDF) 103 Page - Microchip Technology

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