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LSM6DSO16IS Datasheet(PDF) 32 Page - STMicroelectronics |
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LSM6DSO16IS Datasheet(HTML) 32 Page - STMicroelectronics |
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32 / 107 page ![]() 9.3 DRDY_PULSED_REG (0Bh) Pulsed data-ready mode register (R/W) Table 22. DRDY_PULSED_REG register DRDY_ PULSED 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 1. This bit must be set to 0 for the correct operation of the device. Table 23. DRDY_PULSED_REG register description DRDY_PULSED Enables pulsed data-ready mode. (0: Data-ready latched mode (returns to 0 only after an interface reading) (default); 1: Data-ready pulsed mode (the data-ready pulses are 75 µs long)) 9.4 INT1_CTRL (0Dh) INT1 pin control register (R/W) The output of the INT1 pin is the OR combination of the signals selected here and in register MD1_CFG (5Eh). Table 24. INT1_CTRL register 0(1) 0(1) 0(1) 0(1) 0(1) INT1_ BOOT INT1_ DRDY_G INT1_ DRDY_XL 1. This bit must be set to 0 for the correct operation of the device. Table 25. INT1_CTRL register description INT1_ BOOT Boot status available on the INT1 pin. Default value: 0 (0: disabled; 1: enabled) INT1_DRDY_G Enables gyroscope data-ready interrupt on the INT1 pin. Default value: 0 (0: disabled; 1: enabled) INT1_DRDY_XL Enables accelerometer data-ready interrupt on the INT1 pin. Default value: 0 (0: disabled; 1: enabled) LSM6DSO16IS DRDY_PULSED_REG (0Bh) DS13892 - Rev 2 page 32/107 |
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